> >>> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
> >>> error checking enable) must not be changed while the L2 cache is enabled.
> >>> So, L2PE must be set before enabling L2 cache.
> >>
> >> Aneesh,
> >>
> >> The original code set L2PE and L2E together. The L2PE bit doesn't
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, April 19, 2016 10:03 PM
> To: Aneesh Bansal <aneesh.ban...@nxp.com>; u-boot@lists.denx.de
> Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushw.
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
arch/powerpc/cpu/mpc85xx/start.
Define CONFIG_FSL_CAAM for LS2080 which would enable
call to sec_init() during U-Boot.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
include/configs/ls2080a_common.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/ls2080a_common.h b/include/c
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
board/fre
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
arch/arm/cpu/armv8/fsl-laye
Structures have been defined for PDB (Protocol Data Blcks)
for various operations.
These structure will be used to add PDB data while creating
the PDB descriptors.
CC: Ulises Cardenas <raul.ca...@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: A
Construct API's have been added to create Protocol Descriptors
for CAAM block.
CC: Ulises Cardenas <raul.ca...@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
drivers/crypto/fsl/
When CAAM runs a descriptor and an error occurs, a non-zero
value is set in Output Status Register.
The if condition should check the status for a non-zero value.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
drivers/crypto/fsl/jr.c | 2 +-
1 file changed, 1 insertion(+), 1 de
> -Original Message-
> From: york sun
> Sent: Wednesday, February 10, 2016 10:51 AM
> To: Scott Wood <o...@buserror.net>; Aneesh Bansal <aneesh.ban...@nxp.com>
> Cc: u-boot@lists.denx.de; Ruchika Gupta <ruchika.gu...@freescale.com>;
> Prabhakar
com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v4:
- Modified the Commit message
- Functionality moved to SoC Specific file
The pat
> -Original Message-
> From: Huan Wang
> Sent: Tuesday, February 02, 2016 12:31 PM
> To: york sun <york@nxp.com>; Aneesh Bansal <aneesh.ban...@nxp.com>; u-
> b...@lists.denx.de; Huan Wang-B18965 <alison.w...@freescale.com>
> Cc: Ruchika Gupta <ruc
r.kushw...@nxp.com>; Saksham Jain
> <saksham.j...@nxp.com>; Aneesh Bansal <aneesh.ban...@nxp.com>
> Subject: [PATCH v3 15/15] SECURE_BOOT: Enable IE (Key extention) Feature in
> Ls2085a & LS2088a
>
> For validating images from uboot (Such as Kernel Image), either keys fro
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, January 25, 2016 9:06 PM
> To: Aneesh Bansal <aneesh.ban...@nxp.com>
> Cc: u-boot@lists.denx.de; Ruchika Gupta <ruchika.gu...@nxp.com>
> Subject: Re: [U-Boot] [PATCH v3 0/7] D
> -Original Message-
> From: york sun
> Sent: Friday, January 22, 2016 1:52 AM
> To: Aneesh Bansal <aneesh.ban...@nxp.com>; u-boot@lists.denx.de
> Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>
> S
SoC's.
Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining
CONFIG_ENV_IS_NOWHERE
The patches have been tested on LS1043, LS1021, P3041 and T1024.
The patch set is dependent on following:
http://patchwork.ozlabs.org/patch/553826/
Aneesh Bansal (7):
include/configs: make
.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
arch/arm/include/asm/fsl_secure_boot.h | 5 +
include/configs/C29XPCIE.h | 4
include/configs/T102xQDS.h
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
Corrected the macro for SB_EN bit in RCW.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
None (Changed th
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh
variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Protect the inclusion of file fsl_validate.h with macro CONFIG_CHAIN_OF_TRUST
Changes in v2
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
CONFIG_ENV_IS_NOWHERE is defined for Secure Boot
arch/arm/include/asm/fsl_secure_boot.h | 16 ++--
arch/powerpc/include/asm/fsl_secure_boot.h | 41 +-
include/config_fsl_chain_t
(To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Protect the inclusion of file fsl_validate.h with macro CONFIG_CHAIN_OF_TRUST
Changes in v2:
Defconfigs for Secure Boot
have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v4:
Resolved the format specifier warning by printf()
Changes in v3:
Replace the Debug printf() call with debug()
Merged the
to bypass transactions with stream ID other than that of CAAM
b) Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: A
to bypass transactions with stream ID other than taht of CAAM
b_ Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: A
SoC's.
Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining
CONFIG_ENV_IS_NOWHERE
The patches have been tested on LS1043, LS1021, P3041 and T1024.
The patch set is dependent on following:
http://patchwork.ozlabs.org/patch/553826/
Aneesh Bansal (7):
include/configs: make
.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
arch/arm/include/asm/fsl_secure_boot.h | 5 +
include/configs/C29XPCIE.h | 4
include/configs/T102xQDS.h | 12 +++-
include/c
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Corrected the macro for SB_EN bit in RCW.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/as
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
CONFIG_ENV_IS_NOWHERE is defined for Secure Boot
arch/arm/include/asm/fsl_secure_boot.h | 16 ++--
arch/powerpc/include/asm/fsl_secure_boot.h | 41 +-
include/config_fsl_chain_trust.h
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh
(To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Defconfigs for Secure Boot Target are not removed
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4
board/freescale/common/Ma
variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
arch/powerpc/cpu/mpc85xx/cpu_init.c
CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
None (Changed the Sign-Off with New
have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Replace the Debug printf() call with debug()
Merged the two commits into a single commit
Changes in v2:
Replace the
Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Replace the Debug printf() call with debug()
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pa
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
PAMU should not be by-passed in case of Secure Boot.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Modified the commit message
arch/powerpc
to bypass transactions with stream ID other than taht of CAAM
b_ Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: A
Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 449 ++
arch/powerpc/cpu/mpc8xxx/
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
CC: Ruchika Gupta <ruchika.gu...@nxp.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/include/asm/immap_85xx.h | 1 -
2 files changed, 1 ins
environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4
board/freescale/common/Ma
.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
include/configs/C29XPCIE.h | 4
include/configs/T102xQDS.h | 12 +++-
include/configs/T102xRDB.h | 12 +++-
include/configs/T1040QDS.h | 3 ++-
include/configs/T104xRDB.h
For ARM based SoC's there is no need to add a separate target/defconfig
for Secure Boot. Boot Mode can be determined at run time to continue
the chain of trust.
The patch set is dependent on following:
http://patchwork.ozlabs.org/patch/560391/
http://patchwork.ozlabs.org/patch/553826/
Aneesh
CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/include/asm/fsl_secure_boot.h
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh
variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 12
arch/powerpc/include/asm/fsl_secure_boot.
. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/include/asm/fsl_secure_boot.h | 6 +-
arch/powerpc/include/asm/fsl_secure_boot.h | 35 +
board/freescale/common/Makefile
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
arch/p
ed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
CC: Alison Wang <alison.w...@freescale.com>
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index b58f283..a6af95d 100644
--- a/Makefile
+++ b/Makefile
@@ -1136,7 +1136,7 @@ spl/u-b
to the function, the address
field in Header is not read and is treated as a reserved
field.
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/cmd_esbc_validate.c | 10 ++---
board/free
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
New Patch set c
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5:
- Commit Subject modified
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
CC: Alex Porosanu <alexandru.poros...@freescale.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an addi
.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/compiler.h
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5:
- Commit Subject modified
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional
Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/free
on
[PATCH 5/5, v5] drivers/crypto/fsl: fix endianness issue in RNG
http://patchwork.ozlabs.org/patch/553822/
Aneesh Bansal (4):
SECURE BOOT: change prototype of fsl_secboot_validate function
SECURE BOOT: separate functions for reading keys
SECURE BOOT: separate function created for signature
ed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/cmd_esbc_validate.c | 17 -
board/freescale/common/fsl_validate.c | 18 +++---
include/fsl_validate.h | 5 ++---
3 files changed, 25 insertions(+), 15 deleti
The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/fsl_val
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v4:
- Fixed compilation break for LS10
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:
- Enabled CONFIG_SYS_NS1
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/a
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
CC: Alex Porosanu <alexandru.poros...@freescale.com>
---
drivers/crypto/fsl/jr.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/fsl/jr
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/include/asm/arch-fsl-layerscape/co
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch
Commit Subject modified
arch/arm/cpu/arm
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an addi
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch.
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 inse
-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/include/asm/types.h | 2 ++
arch/powerpc/include/asm/types.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 388058e..765 100644
--- a/arch/arm/include/asm/t
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
CC: Alex Porosanu <alexandru.poros...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch.
drivers/crypto/fsl/jr.c | 8 ++--
1 file changed, 2 inse
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.
Signed-off-by: Lawish Deshmukh <lawish.deshm...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/fsl_validate.c | 2 +-
1 fil
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:
Corrected the definition of virt_to_phys() and definition of phys_addr_t.
arch/arm/include/asm/io.h| 4 ++--
arch/arm/i
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
Compile time
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
There is no need for defining 64 bit I/O operations.
If an IP needs to do 64 bit access, it will do it by defining
32 bit addr_hi
to Job Rings are done
using I/O functions defined for SEC which will take care of
the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
Compile time
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v8:
New Patchset Created
.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v8:
New Patchset Created
Makefile | 4
arch/powerpc/cpu/mpc85xx/start.S | 11 +++
arch/powerpc/include/asm/fsl_secure_boot.h | 5 +
board/freescale/common
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v8:
New Patchset Created
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4
3 files changed, 10 insertions(+)
create mode
Data types and I/O functions have been defined for
64 bit physical addresses in arm and powerpc
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
arch/arm/include/asm/io.h | 4 +++-
arch/arm/include/asm/types.h | 13 -
arch/powerpc/include/asm/io.h | 13
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
board/freescale/common
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
board/freescale/common
arch-ls102xa/config.h to
arm/include/asm/fsl_secure_boot.h
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v8:
New Patch added in patchset
arch/arm/include/asm/arch-ls102xa/config.h | 14 --
arch/arm/include/asm/fsl_secure_boot.h | 22
using I/O functions
defined for SEC which will take care of the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
drivers/crypto/fsl/desc_constr.h | 24
...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v7:
Patchset created.
arch/powerpc/include/asm/fsl_secure_boot.h | 14 ++
include/config_fsl_secboot.h | 29 -
include/configs/corenet_ds.h | 1 +
3
-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v7:
Patchset created.
TEXT BASE is defined as 0xFFF4 as per new design.
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
.
Signed-off-by: Saksham Jain saks...@freescale.com
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v7:
Created TLB entry to map virtual address 0xFFF0 to physical address
0xBFF0 as per discussion.
Makefile
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v6:
Changed the version in Patchset.
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4
3 files changed, 10 insertions
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
New patch set created.
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4
3 files changed, 10 insertions(+)
create
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4
3 files changed, 10 insertions(+)
create mode 100644 configs
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
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