For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.
Signed-off-by: Chen-Yu Tsai <w...@csie.
On Thu, May 19, 2016 at 4:40 PM, Hongbo Zhang <macro.wav...@gmail.com> wrote:
> On Wed, May 18, 2016 at 5:19 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> Hi,
>>
>> On Wed, May 18, 2016 at 5:10 PM, <macro.wav...@gmail.com> wrote:
>>> From: Wang Dong
Hi,
On Wed, May 18, 2016 at 5:10 PM, wrote:
> From: Wang Dongsheng
>
> According to PSCI specification v1.0, the PSCI functions should start from
> 0x8400 for SMC32, this patch changes this base value as well as other
> function offset
Hi,
On Wed, May 18, 2016 at 5:10 PM, wrote:
> From: Hongbo Zhang
>
> The input parameter CPU ID needs to be validated before furher oprations such
> as CPU_ON, this patch introduces the function to do this.
Could you generalize this patch for all
Hi,
On Wed, May 18, 2016 at 3:34 AM, wrote:
> Updated to address concerns raised on mailing list.
>
> I won't have time to work on this further for a while; please feel free to
> use / merge anything from the series that
> is acceptable. I'll try to make time
On Wed, May 18, 2016 at 3:25 AM, Timothy Pearson
<tpear...@raptorengineering.com> wrote:
> On 05/17/2016 12:27 AM, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, May 17, 2016 at 10:39 AM, <tpear...@raptorengineering.com> wrote:
>>
>> Description please.
On Wed, May 18, 2016 at 3:19 AM, Timothy Pearson
<tpear...@raptorengineering.com> wrote:
> On 05/17/2016 12:21 AM, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, May 17, 2016 at 10:38 AM, <tpear...@raptorengineering.com> wrote:
>>> ---
>>> arch/arm/c
Hi,
On Tue, May 17, 2016 at 10:39 AM, wrote:
Description please. How did you learn of the different revisions?
Any differences between the revisions?
> Signed-off-by: Timothy Pearson
> ---
> arch/arm/mach-sunxi/cpu_info.c |
Hi,
On Tue, May 17, 2016 at 10:39 AM, wrote:
Description please.
> Signed-off-by: Timothy Pearson
> ---
> arch/arm/cpu/armv7/sunxi/Makefile | 1 +
> arch/arm/cpu/armv7/sunxi/tzpc.c| 10 ++
>
Hi,
On Tue, May 17, 2016 at 10:38 AM, wrote:
> ---
> arch/arm/cpu/armv7/psci.S | 1 +
> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 4 ++--
> 3 files changed, 5 insertions(+), 4 deletions(-)
>
> diff
Hi,
On Tue, May 17, 2016 at 10:38 AM, wrote:
A commit message would be nice.
> Signed-off-by: Timothy Pearson
> ---
> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On Thu, May 5, 2016 at 6:36 AM, André Przywara wrote:
> On 04/05/16 23:15, Peter Robinson wrote:
>> On Wed, May 4, 2016 at 11:05 PM, André Przywara
>> wrote:
>>> On 04/05/16 22:53, Peter Robinson wrote:
On Wed, May 4, 2016 at 10:15 PM, Andre
The A80 uses the AXP809 as its primary PMIC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Without actual SPL support, this patch has only been compile tested.
---
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/pmic_bus.c | 6 +-
board/sunxi/board.c
The SW output of the PMIC supplies the ethernet PHY with power.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/Sinovoip_BPI_M3_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/Sinovoip_BPI_M3_defconfig
b/configs/Sinovoip_BPI_M3_defconfig
index 13dbb9
Adds poweroff support for axp818 pmic.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/power/Kconfig | 1 +
drivers/power/axp818.c | 11 +++
include/axp818.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
The AXP818 has a switchable output, SW. This is commonly used for
controlling power to the LCD backlight.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/board.c| 1 +
drivers/power/Kconfig | 7 +++
drivers/power/axp818.c | 10 ++
include/axp818.h
The user should always select an SoC variant to support. Not choosing
one doesn't make sense for a bootloader.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index fa7872
The ELDO enable bits and registers are contiguous for axp221. Instead
of a switch case testing against the index, just use the index to shift
the bit or register offset.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/power/axp221.c | 27 +++
1 file chan
The newer chips use a newer display pipeline, which is not supported.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index a24d5c238da9..059e9146cc5c
Description said eldo2 instead of fldo2, a copy-paste error.
Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs")
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/power/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/K
A83T, H3, and A64 have a dedicated pin for card detect on the PF
pingroup. This is used in all designs. Set it as the default.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
In most other places, we sort SoC descriptions by family (sunXi) first,
then by the chip name (A20).
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/Kconfig | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/board/sunxi/Kconfig b/board
On Thu, Mar 31, 2016 at 10:59 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
> On 29-03-16 18:26, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds more support for axp818 regulators, and USB support
>> for A83T. Normal EHCI/OHCI USB
We have a separate compatible for almost each SoC. Add one for the A83T.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/usb/host/ohci-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index d4fb95a..6f3f4ce
This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git
This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12
1 file changed, 12 insertions(+)
diff
This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12
1 file changed, 12 insertions(+)
diff --git
The h8_homlet_v2 has 2 USB host ports, one connected to the OTG
controller, one connected to the EHCI/OHCI pair.
Also provide the card detect pin for MMC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 5 +
1 file changed, 5 insertions(+)
diff
AXP818 supports VBUS drive function, even though the manual does not
mention it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/axp818.h b/include/axp818.h
index 003477f..5630eed
Like the Allwinner A33 SoC, the A83T is missing the config register
from the musb USB DRD hardware block. Use a known working value for
it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/usb/musb-new/musb_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
-by: Chen-Yu Tsai <w...@csie.org>
---
configs/Cubietruck_plus_defconfig | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/configs/Cubietruck_plus_defconfig
b/configs/Cubietruck_plus_defconfig
index bb0b336..d625c21 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/c
We have a separate compatible for almost each SoC. Add one for the A83T.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/usb/host/ehci-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 677a5d3..d5eb492
VBUS drive is supported on AXP221 and later PMICs. Rework the macros
so we can support this on later PMICs without too much work.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/gpio/axp_gpio.c | 25 ++---
include/axp221.h| 8
2 files chang
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/as
DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY /
composite video encoder.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++
include/configs/sun8i.h| 2 ++
2 files changed, 50 inse
The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY
on the A83T/H8.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/board.c| 6 ++
drivers/power/Kconfig | 27 +++
drivers/power/axp818.
DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3,
1.35V for DDR3L, and 1.2V for LPDDR3.
Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 1 -
drivers/power/Kconfig
enables USB Kconfig options in Cubietruck_plus_defconfig.
Patch 15 ~ 17 is the minimal changes needed to enable USB on the
A83T boards I have. They are not the same as the kernel changes
I will submit, and should not be merged without discussion.
Regards
ChenYu
Chen-Yu Tsai (17):
power: axp818
axp818_init() is declared, but never defined.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/axp818.h b/include/axp818.h
index 46d05ad..c2f9847 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -53,8
The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some
Allwinner-based boards set it to 3.0V to conserve power. Since the
h8_homlet_v2 is a set-top box board with external power, there is
no such requirement.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_def
Hi,
On Thu, Mar 24, 2016 at 2:46 PM, Michael Haas wrote:
>
> This patch is required to get reliable 1000BASE-T operation on some
> boards using the RTL8211C(L) PHY.
>
> Following discussions on v2 of this patch, I have removed the incorrect
> check for the RTL8211C(L).
Hi,
On Sun, Mar 20, 2016 at 3:52 PM, Michael Haas wrote:
> Hello all,
>
> I'd like to add some device-specific hacks to realtek.c. I'm using the
> Olimex A20-OlinuXino-Lime2 which uses the RTL8211CL PHY.
>
> Which of the various phy_driver structs is responsible for
Hi,
On Mon, Mar 21, 2016 at 6:18 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
>
> On 21-03-16 11:06, Chen-Yu Tsai wrote:
>>
>> Hi,
>>
>> On Mon, Mar 21, 2016 at 5:57 PM, Hans de Goede <hdego...@redhat.com>
>> wrote:
>
Hi,
On Mon, Mar 21, 2016 at 5:57 PM, Hans de Goede wrote:
> HI,
>
>
> On 21-03-16 10:49, wens Tsai wrote:
>>
>> Hi Hans,
>>
>> I updated U-boot on my boards to your latest sunxi-wip branch:
>>
>> f965340 ("sunxi: Enable support for the eMMC found on the orangepi
>>
, audio jacks, 2 tablet-like volume
buttons, RS232 style UART and USB OTG (though VBUS is not connected).
Various headers are available for other addon modules, such as SDIO
WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board
Hi,
On Sun, Mar 20, 2016 at 9:21 PM, Hans de Goede wrote:
> This enables support for the eMMC found on the orangepi plus.
>
> Signed-off-by: Hans de Goede
> ---
> configs/orangepi_plus_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
Hi,
On Wed, Feb 10, 2016 at 5:25 PM, Hans de Goede wrote:
> From: Jelle van der Waa
>
> Add support for phy 1-3.
>
> Signed-off-by: Jelle van der Waa
> [hdego...@redhat.com: use setclrbits_le32 instead of read-modify-write]
> Signed-off-by:
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
1 file changed, 7 insertions(+)
which holds the MAC address.
DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
is connected to the reset control of the PHY. EMAC is not actually
supported yet.
The DTS is the same as the one already in the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/Ma
axp221 dldo functions into 1.
Patch 3 adds support for axp818's dldos and eldos.
Patch 4 drops the LDO voltages from h8_homlet_v2_defconfig. These
match the defaults.
Patch 5 adds support for axp818's aldos.
Regards
ChenYu
Chen-Yu Tsai (5):
power: axp818: Remove duplicate register definition
.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/board.c| 8 +++-
drivers/power/Kconfig | 13 ++---
drivers/power/axp818.c | 37 +
3 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/board/sunxi/board.c b/board
Instead of one function for each DLDO regulator, make 1 function that
takes an extra "index". Since the control bits for the DLDO regulators
are contiguous, this makes the function very simple. This removes a lot
of duplicate code.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Some of the register definitions are duplicated. Drop them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 8
1 file changed, 8 deletions(-)
diff --git a/include/axp818.h b/include/axp818.h
index 1dc6456..46d05ad 100644
--- a/include/axp818.h
+++ b/include/ax
AXP818 provides an array of LDOs to provide power to various peripherals.
None of these regulators are critical.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/power/Kconfig | 12 ++--
drivers/power/axp818.c | 44
2 files chang
The LDO settings in this defconfig are either wrong (ALDOs must not be 0)
or the same as Kconfig defaults.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 3 ---
1 file changed, 3 deletions(-)
diff --git a/configs/h8_homlet_v2_defconfig b/c
Hi,
On Tue, Jan 12, 2016 at 1:21 AM, Vishnu Patekar
wrote:
> Add dts and defconfig for Banana-pi M3 board.
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> mic, AP6212 Wifi, etc on it.
> It is paired with AXP813 PMIC which is almost same as
(weak) empty function so things do
not break.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/clock.c | 5 +
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 13 +
arch/arm/include/asm/arch-sunxi/clock.h | 1 +
arch/arm/include/as
access.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/tzpc.c| 11 ++-
arch/arm/include/asm/arch-sunxi/tzpc.h | 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu
/ tested by Siarhei.
Patch 4 enables PSCI support for the H3 in Kconfig.
I've only tested booting HYP/SMP on my Orange Pi PC. Hotplugging was not
tested, but should work.
Regards
ChenYu
Chen-Yu Tsai (4):
sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3
sunxi: Support H3 CCU
H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
Now that we support PSCI and various security switches, we can let
U-boot boot Linux into non-secure and HYP mode.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9
On Mon, Dec 28, 2015 at 1:16 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Wed, Dec 23, 2015 at 12:14:15PM +0200, Siarhei Siamashka wrote:
>> On Tue, 17 Nov 2015 15:32:30 +0100
>> Jens Kuske <jensku...@gmail.com> wrote:
>>
>> > On 16/
On Wed, Dec 23, 2015 at 6:14 PM, Siarhei Siamashka
<siarhei.siamas...@gmail.com> wrote:
> On Tue, 17 Nov 2015 15:32:30 +0100
> Jens Kuske <jensku...@gmail.com> wrote:
>
>> On 16/11/15 07:26, Chen-Yu Tsai wrote:
>> > Hi everyone,
>> >
>> > I got
Hi,
On Sun, Nov 22, 2015 at 11:40 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
> On 22-11-15 15:14, Chen-Yu Tsai wrote:
>>
>> On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <ijc+ub...@hellion.org.uk>
>> wrote:
>>>
>>&g
gt;> and gives us a nice speed-up in certain workloads.
>>
>> Suggested-by: Chen-Yu Tsai <w...@csie.org>
>> Signed-off-by: Hans de Goede <hdego...@redhat.com>
>
> I suppose you've tested this on at least one such board? In that case:
> Acked-by: Ian Cam
On Fri, Nov 20, 2015 at 11:40 PM, Hans de Goede wrote:
> Hi,
>
> On 20-11-15 06:07, Siarhei Siamashka wrote:
>>
>> The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
>> on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
>> This can be verified by
Hi everyone,
(Resent with my correct email address...)
I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
includes Jens' patches.
For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
The CPUCFG registers line up. The manual doesn't have the
Hi,
On Sun, Nov 15, 2015 at 2:47 AM, Vishnu Patekar
wrote:
> Hello,
>
> On Sat, Nov 14, 2015 at 1:25 AM, Hans de Goede wrote:
>> Hi,
>>
>> On 12-11-15 19:09, Vishnu Patekar wrote:
>>>
>>> Add basic clocks pll1, pll5, and some default values from
On Sat, Nov 14, 2015 at 12:52 AM, Hans de Goede wrote:
> Hi,
>
> On 12-11-15 19:09, Vishnu Patekar wrote:
>>
>> This patch series adds basic support for Allwinner A83T SOC.
>>
>> Allwinner A83T is octa-core cortex-a7 based SoC.
>> It's clock control unit and prcm, pinmux are
On Sat, Oct 3, 2015 at 10:26 PM, Hans de Goede wrote:
> Change the axp223 dcdc2 / VDD-SYS default from 1.2V to 1.1V, 1.1V is the
> value recommended by Allwinner and is what most fex files specify.
>
> This has been tested on a number of A23/A33 tablets including on an
> A23
t; > > Hi,
>> > >
>> > > On 03-10-15 16:32, Chen-Yu Tsai wrote:
>> > > > On Sat, Oct 3, 2015 at 10:26 PM, Hans de Goede <hdego...@redhat.com
>> > > > >
>> > > > wrote:
>> > > > > Stop prefix
On Sat, Oct 3, 2015 at 10:26 PM, Hans de Goede wrote:
> Stop prefixing the axp functions for setting voltages, etc. with the
> model number, there ever is only one pmic driver built into u-boot,
> this allows simplifying the callers.
Hmm... What's going to happen with the
On Fri, Sep 25, 2015 at 4:06 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
> On 25-09-15 04:35, Chen-Yu Tsai wrote:
>>
>> On Thu, Sep 24, 2015 at 11:24 PM, Hans de Goede <hdego...@redhat.com>
>> wrote:
>
>
>
>
>>> diff -
On Thu, Sep 24, 2015 at 11:24 PM, Hans de Goede wrote:
> The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
> chinese tablets. There are some differences in which accelerometer /
> wifi is used, but other then that these are all the same from a u-boot /
On Tue, Aug 25, 2015 at 3:34 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On Tue, 25 Aug 2015 10:49:19 +0800
Chen-Yu Tsai w...@csie.org wrote:
Hi,
Thanks for putting this patch together. A few comments below:
On the A31s the RTC is by default secured. Thus when u-boot
loads the kernel
register contents do not affect access to the RTC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/board.c | 5 +
arch/arm/cpu/armv7/sunxi/tzpc.c| 18 ++
arch/arm/include/asm/arch-sunxi/tzpc.h
On Sun, Aug 16, 2015 at 5:39 PM, Hans de Goede hdego...@redhat.com wrote:
Add CONFIG_MMC0_CD_PIN to various boards, this stoos the SPL from still
^
stops
trying to access the sdcard when there
On Sun, Aug 16, 2015 at 4:02 AM, Hans de Goede hdego...@redhat.com wrote:
nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for overshooting up to
On Sat, Aug 8, 2015 at 10:25 PM, Hans de Goede hdego...@redhat.com wrote:
Add support for the mipi pll, this is necessary for getting higher dotclocks
with lcd panels.
Do you plan on adding this to the kernel (both the clock driver and reference
in the simplefb node) as well?
ChenYu
On Mon, Jul 6, 2015 at 3:15 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 29-06-15 11:47, 加特技的肖特基 wrote:
From 83aa308eb836b0a63f0e30bd10d72040151a1e98 Mon Sep 17 00:00:00 2001
From: Zhi Yuan Wan dv...@qq.com
Date: Thu, 25 Jun 2015 20:00:46 +0800
Subject: [PATCH 2/3] sunxi:Added Mele
to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Cc: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/cpu
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/dts/Makefile| 3 ++-
board/sunxi/MAINTAINERS | 6
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/dts/sun8i-a23-a33.dtsi| 10 ++
...sun8i-a33.dtsi = sun8i
.
Patch 3 adds support for UART0 on PB pin group, which is A33 specific.
Patch 4 syncs the sun8i dts files with the latest dts patches bound
for 4.2.
Patch 5 adds a defconfig for the Sinlinx SinA33.
Regards
ChenYu
Chen-Yu Tsai (5):
sunxi: hardware-feature-specific function index defines for PORT F
Commit 487b327 (sunxi: GPIO pin mux hardware-feature-specific function
index defines) renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 8
1 file changed, 4 insertions(+), 4
Hi,
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass s...@chromium.org wrote:
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
The subject line should probably reflect this is a DWMMC only
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass s...@chromium.org wrote:
These bloat the code and cause problems for SPL. Use debug() where possible
and try to return a useful error code instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
Hi,
On Wed, May 13, 2015 at 6:12 AM, Tom Rini tr...@konsulko.com wrote:
On Tue, May 12, 2015 at 02:46:24PM -0500, Joe Hershberger wrote:
In order to reduce merge conflicts and to maintain the simplest possible
defconfig files, we should be using the savedefconfig feature of Kconfig
every
On Thu, May 28, 2015 at 11:22 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote:
This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu
Hi,
On Thu, May 28, 2015 at 11:31 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Chen-Yu,
On Thu, May 28, 2015 at 09:25:26PM +0800, Chen-Yu Tsai wrote:
Hi everyone,
I finally got around to rebasing and fixing up my PSCI stuff.
This series adds PSCI support for sun6i and sun8i
On Thu, May 28, 2015 at 11:23 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, May 28, 2015 at 09:25:29PM +0800, Chen-Yu Tsai wrote:
The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.
Also explain lock cpu
The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.
This paves the way for adding PSCI support for other platforms.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 2 +-
arch/arm/cpu/armv7
sun8i uses the same PSCI backend as sun6i, without power clamps.
Since there is no secure SRAM, the backend is placed at the end
of DRAM.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
board/sunxi/Kconfig | 6 ++
include/configs/sun8i.h | 6 ++
2 files changed, 12 insertions(+)
diff
The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.
Also explain lock cpu and unlock cpu as enabling/disabling
debug access.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/psci.S | 14 +++---
1 file
This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++
2 files changed, 277 insertions(+)
create
Now that we have a PSCI backend for sun6i, enable it.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
board/sunxi/Kconfig | 3 +++
include/configs/sun6i.h | 5 +
2 files changed, 8 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c6c876d..64d2af8 100644
sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4
2 files changed, 5 insertions(+)
diff --git
to the SPL for loading u-boot
from internal NAND memory)
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
board/sunxi/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3f23f26..f27967b 100644
--- a/board/sunxi/board.c
+++ b
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