On 1 August 2014 15:29, Andre Przywara wrote:
>
>
> On 01/08/14 14:02, Christoffer Dall wrote:
>> On 1 August 2014 14:59, Andre Przywara wrote:
>>>
>>>
>>> On 01/08/14 13:53, Christoffer Dall wrote:
>>>> On 1 August 2014 14:46, Andreas Fä
On 1 August 2014 14:59, Andre Przywara wrote:
>
>
> On 01/08/14 13:53, Christoffer Dall wrote:
>> On 1 August 2014 14:46, Andreas Färber wrote:
>>> Hi,
>>>
>>> Am 01.08.2014 13:35, schrieb Christoffer Dall:
>>>> From: Andre Przywar
On 1 August 2014 14:46, Andreas Färber wrote:
> Hi,
>
> Am 01.08.2014 13:35, schrieb Christoffer Dall:
>> From: Andre Przywara
>>
>> To enable hypervisors utilizing the ARMv7 virtualization extension
>> on the Arndale board, add the simple SMP pen address writer
directly from u-boot.
Reviewed-by: Christoffer Dall
Signed-off-by: Andre Przywara
---
Note that Andre previously reported a board reset on initial boot with
this patch, but I have applied this patch on upstream master of U-Boot
and tested on two separate Arndale boards and it boots perfectly fine
and
On 29 December 2013 21:15, wrote:
> Hi, Dall:
> Thanks for your quick response!
>>It depends on the board. Which ARM doc are you referring to?
> ARM Security Technology : Building a Secure System using TrustZone
> Technology.
> (PRD29-GENC-009492C)
> Figure 5-2 in Chapter 5.2.1 Boot Sequence.
>
On 29 December 2013 19:10, wrote:
> Hi, Dall:
> I have a few questions about switching cpu's state from secure to
> non-sec in uboot.
> 1. I found do_nonsec_virt_switch() function had been integrated in
> uboot_2014_01_RC2.
> This function would switch cpu from secure state to non-sec, even
>
On Fri, Nov 22, 2013 at 10:56:05AM +, Marc Zyngier wrote:
> On 22/11/13 01:51, Christoffer Dall wrote:
> > On 21 November 2013 00:59, Marc Zyngier wrote:
> >> A CP15 instruction execution can be reordered, requiring an
> >> isb to be sure it is executed in program
On Fri, Nov 22, 2013 at 02:30:27PM +0530, Anup Patel wrote:
> On Fri, Nov 22, 2013 at 2:12 PM, Ian Campbell wrote:
> > On Fri, 2013-11-22 at 09:28 +0530, Anup Patel wrote:
> >> An Independent binary of a secured firmware makes more sense here.
> >> Also, if secured firmware is an independent binar
On 21 November 2013 07:04, Marc Zyngier wrote:
> Hi Rob,
>
> On 21/11/13 14:28, Rob Herring wrote:
>> On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
>>> PSCI is an ARM standard that provides a generic interface that
>>> supervisory software can use to manage power in the following
>>> situa
On 21 November 2013 00:59, Marc Zyngier wrote:
> A CP15 instruction execution can be reordered, requiring an
> isb to be sure it is executed in program order.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm/cpu/armv7/nonsec_virt.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/ar
On 12 November 2013 22:22, Albert ARIBAUD wrote:
> Hi Christoffer,
>
> On Tue, 12 Nov 2013 14:34:00 -0800, Christoffer Dall
> wrote:
>
>> On 12 November 2013 13:29, Albert ARIBAUD wrote:
>> > Hi Christoffer,
>> >
>> > On Tue, 12 Nov 2
On 12 November 2013 13:29, Albert ARIBAUD wrote:
> Hi Christoffer,
>
> On Tue, 12 Nov 2013 09:09:23 -0800, Christoffer Dall
> wrote:
>
>> I suspect that if you are in Hyp mode, you should not worry about
>> FIQ/IRQ mode, but just make sure to configure Hyp mode prope
On 12 November 2013 08:53, Andre Przywara wrote:
> On 11/12/2013 05:28 PM, Christoffer Dall wrote:
>>
>> On 12 November 2013 03:41, Albert ARIBAUD
>> wrote:
>>>
>>> (Cc:ing Andre and Christoffer as they have discussed HYP on the ML.)
>>>
>>
On 12 November 2013 03:41, Albert ARIBAUD wrote:
> (Cc:ing Andre and Christoffer as they have discussed HYP on the ML.)
>
> Hello,
>
> I am working on changing the way IRQ/FIQ stacks are set up, from
> "on-the-fly in a hurry while in the handler" to "during init, so that
> when entering the handle
On Thu, Oct 03, 2013 at 08:24:57AM +0200, Albert ARIBAUD wrote:
> Hi Andre,
>
> On Thu, 19 Sep 2013 18:06:45 +0200, Andre Przywara
> wrote:
>
> > For the KVM and XEN hypervisors to be usable, we need to enter the
> > kernel in HYP mode. Now that we already are in non-secure state,
> > HYP mode s
On Fri, Sep 20, 2013 at 08:08:45AM +0530, Mj Embd wrote:
> On Fri, Sep 20, 2013 at 6:12 AM, Christoffer Dall <
> christoffer.d...@linaro.org> wrote:
>
> > On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
> > > Just checking, is the mcr p15,0,r1,c1,c1,0 in sy
On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
> Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following text
> . I could be wrong here, just checking
In the future, if you can comment specifically inline on the lines of
code you are targeting, it is easier for other people
On Fri, Sep 20, 2013 at 01:27:48AM +0530, Mj Embd wrote:
> two quick points
> (a) xen already has a mode_switch code, so AFAIK xen might not use it
> (as suggested by comment in another patch in this patch set)
For KVM the boot procedure for Hyp mode is quite clearly defined: the
kernel must be bo
On Thu, Sep 19, 2013 at 10:00:03PM +0530, Mj Embd wrote:
> Hi Andre,
>
> There is another approach taken in xen. (xen/arch/arm/mode_switch.S)
> Which do you think is the better approach
>
Hi there,
I'm not sure I completely understand your question. Do you think this
patch series should be chan
On Mon, Aug 26, 2013 at 05:30:14PM -0400, Tom Rini wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 08/26/2013 04:51 PM, Christoffer Dall wrote:
> > On Fri, Aug 16, 2013 at 03:53:01PM +0200, Andre Przywara wrote:
> >
> > [...]
> >
> >>
On Fri, Aug 16, 2013 at 03:53:01PM +0200, Andre Przywara wrote:
[...]
>
> Albert, Tom,
> do you need more ACKs or Reviewed-bys?
>
Albert, Tom,
Can you let us know if you will accept a pull request for these patches?
They look to be in pretty good shape?
Thanks!
-Christoffer
_
On Fri, Aug 09, 2013 at 05:03:08PM +0200, Andre Przywara wrote:
> The core specific part of the work is done in the assembly routine
> in nonsec_virt.S, introduced with the previous patch, but for the full
> glory we need to setup the GIC distributor interface once for the
> whole system, which is
On Fri, Aug 09, 2013 at 05:03:11PM +0200, Andre Przywara wrote:
> For the KVM and XEN hypervisors to be usable, we need to enter the
> kernel in HYP mode. Now that we already are in non-secure state,
> HYP mode switching is within short reach.
>
> While doing the non-secure switch, we have to enab
in the respective functions and getting
> rid of the error code enum at all (by popular demand ;-)
> * minor style fixes
>
> Please review and comment!
>
Only had those very few nits sent separately, which can be fixed later
if we want. Otherwise looks good.
Reviewed-by: Christoffer Dall
Thanks,
-Christoffer
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On Tue, Jul 30, 2013 at 01:32:14PM +0200, Andre Przywara wrote:
> On 07/30/2013 12:02 AM, Christoffer Dall wrote:
> >On Wed, Jul 10, 2013 at 01:54:16AM +0200, Andre Przywara wrote:
> >
> >[...]
> >
> >>diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm
On Tue, Jul 30, 2013 at 01:59:29PM +0200, Andre Przywara wrote:
> On 07/30/2013 12:02 AM, Christoffer Dall wrote:
> >On Wed, Jul 10, 2013 at 01:54:18AM +0200, Andre Przywara wrote:
[...]
> >>
> >>+_hyp_trap:
> >>+ mrs lr, elr_hyp @ for old
On Tue, Jul 30, 2013 at 01:51:33PM +0200, Andre Przywara wrote:
> On 07/30/2013 12:02 AM, Christoffer Dall wrote:
> >On Wed, Jul 10, 2013 at 01:54:17AM +0200, Andre Przywara wrote:
> >>Currently the non-secure switch is only done for the boot processor.
> >>To enable f
n Wed, Jul 10, 2013 at 01:54:14AM +0200, Andre Przywara wrote:
> A prerequisite for using virtualization is to be in HYP mode, which
> requires the CPU to be in non-secure state first.
> Add new file in arch/arm/cpu/armv7 to hold a monitor handler routine
> which switches the CPU to non-secure stat
On Wed, Jul 10, 2013 at 01:54:17AM +0200, Andre Przywara wrote:
> Currently the non-secure switch is only done for the boot processor.
> To enable full SMP support, we have to switch all secondary cores
> into non-secure state also.
>
> So we add an entry point for secondary CPUs coming out of low
On Wed, Jul 10, 2013 at 01:54:18AM +0200, Andre Przywara wrote:
> For the KVM and XEN hypervisors to be usable, we need to enter the
> kernel in HYP mode. Now that we already are in non-secure state,
> HYP mode switching is within short reach.
>
> While doing the non-secure switch, we have to enab
On Wed, Jul 10, 2013 at 01:54:16AM +0200, Andre Przywara wrote:
[...]
> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
> index 1b6e0ac..7b0619e 100644
> --- a/arch/arm/lib/bootm.c
> +++ b/arch/arm/lib/bootm.c
> @@ -34,6 +34,10 @@
> #include
> #include
>
> +#ifdef CONFIG_ARMV7_NONS
On Thu, Jun 13, 2013 at 01:01:12PM +0200, Andre Przywara wrote:
> For the KVM and XEN hypervisors to be usable, we need to enter the
> kernel in HYP mode. Now that we already are in non-secure state,
> HYP mode switching is within short reach.
>
> While doing the non-secure switch, we have to enab
On Thu, Jun 13, 2013 at 01:01:11PM +0200, Andre Przywara wrote:
> Currently the non-secure switch is only done for the boot processor.
> To enable full SMP support, we have to switch all secondary cores
> into non-secure state also.
>
> So we add an entry point for secondary CPUs coming out of low
On Thu, Jun 13, 2013 at 01:01:09PM +0200, Andre Przywara wrote:
> While actually switching to non-secure state is one thing, the
> more important part of this process is to make sure that we still
super nit: not sure it's more important - it's just another thing we
need to do.
> have full access
On Thu, Jun 13, 2013 at 01:01:10PM +0200, Andre Przywara wrote:
> To actually trigger the non-secure switch we just implemented, call
> the switching routine from within the bootm command implementation.
> This way we automatically enable this feature without further user
> intervention.
>
> The c
On Fri, May 31, 2013 at 11:34:38AM +0200, Andre Przywara wrote:
> On 05/31/2013 07:43 AM, Christoffer Dall wrote:
> >On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
> >>For the KVM and XEN hypervisors to be usable, we need to enter the
> >>kernel in HY
On Fri, May 31, 2013 at 11:32:40AM +0200, Andre Przywara wrote:
> On 05/31/2013 07:32 AM, Christoffer Dall wrote:
> > On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
> >> Currently the non-secure switch is only done for the boot processor.
> >> To later
On Fri, May 31, 2013 at 11:30:32AM +0200, Andre Przywara wrote:
> On 05/31/2013 07:10 AM, Christoffer Dall wrote:
> >On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
> >>To actually trigger the non-secure switch we just implemented, call
> >>the switch
On Fri, May 31, 2013 at 08:36:12AM +0200, Andre Przywara wrote:
> On 05/31/2013 08:11 AM, Christoffer Dall wrote:
> > On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
> >> (for GIT URL and Changelog see below)
> >>
> >> ARM CPUs with the virt
On Fri, May 31, 2013 at 11:26:06AM +0200, Andre Przywara wrote:
> On 05/31/2013 05:04 AM, Christoffer Dall wrote:
> >On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
> >>While actually switching to non-secure state is one thing, the
> >>more important part
On Fri, May 31, 2013 at 11:23:16AM +0200, Andre Przywara wrote:
> On 05/31/2013 03:02 AM, Christoffer Dall wrote:
>
> Christoffer,
>
> thanks a lot for the thorough review. Comments inline.
>
> >On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
>
On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
> (for GIT URL and Changelog see below)
>
> ARM CPUs with the virtualization extension have a new mode called
> HYP mode, which allows hypervisors to safely control and monitor
> guests. The current hypervisor (KVM and Xen) implementat
On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
> For the KVM and XEN hypervisors to be usable, we need to enter the
> kernel in HYP mode. Now that we already are in non-secure state,
> HYP mode switching is within short reach.
>
> While doing the non-secure switch, we have to enab
On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
> Currently the non-secure switch is only done for the boot processor.
> To later allow full SMP support, we have to switch all secondary
> cores into non-secure state also.
>
> So we add an entry point for secondary CPUs coming out o
On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
> To actually trigger the non-secure switch we just implemented, call
> the switching routine from within the bootm command implementation.
> This way we automatically enable this feature without further user
> intervention.
>
> Some
On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
> While actually switching to non-secure state is one thing, the
> more important part of this process is to make sure that we still
> have full access to the interrupt controller (GIC).
> The GIC is fully aware of secure vs. non-secur
On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
> A prerequisite for using virtualization is to be in HYP mode, which
> requires the CPU to be in non-secure state.
> Introduce a monitor handler routine which switches the CPU to
> non-secure state by setting the NS and associated bit
On Mon, May 06, 2013 at 03:19:40PM +0200, Andre Przywara wrote:
> On 04/27/2013 12:13 AM, Christoffer Dall wrote:
> >On Fri, Apr 26, 2013 at 6:14 AM, Andre Przywara
> > wrote:
> >>Currently the non-secure switch is only done for the boot processor.
> >>To later a
On Fri, Apr 26, 2013 at 6:14 AM, Andre Przywara
wrote:
> Currently the non-secure switch is only done for the boot processor.
> To later allow full SMP support, we have to switch all secondary
> cores into non-secure state also.
>
> So we add an entry point for secondary CPUs coming out of low-pow
On Fri, Apr 26, 2013 at 03:14:54PM +0200, Andre Przywara wrote:
> A prerequisite for using virtualization is to be in HYP mode, which
> requires the CPU to be in non-secure state.
> According to the ARM ARM this should not be done in SVC mode, so we
> have to setup a SMC handler for this. We reuse
On Fri, Apr 26, 2013 at 7:14 AM, Andre Przywara
wrote:
> On 04/26/2013 03:42 PM, Peter Maydell wrote:
>> On 26 April 2013 14:24, Andre Przywara wrote:
>>> On 04/26/2013 03:18 PM, Peter Maydell wrote:
The obvious question here is "why do we need a new command?".
The kernel booting specif
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