If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
mapped access will be used to read/write the uart registers.
This is especially useful for SoC devices that implement 16550
compatible uarts but that have peripheral access width constraints.
Signed-off-by: Dave Aldridge
---
drivers
Picochip picoXcell based
development platform.
Dave Aldridge (4):
macb: initial support for Cadence GEM
macb: support higher rate GEM MDIO clock divisors
macb: support DMA bus widths > 32 bits
macb: allow GEM to have configurable receive buffer size
drivers/net/macb.c |
register base register
locations in GEM.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 18 +++-
drivers/net/macb.h | 55
2 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on the
device type.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 63 ++--
drivers/net/macb.h | 12 ++
2
Some GEM implementations may support DMA bus widths up to 128 bits.
We can get the maximum supported DMA bus width from the design
configuration register so use that to program the device up.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 25 +
drivers/net
GEM has configurable receive buffer sizes so requires this to be
programmed up.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 19 +++
drivers/net/macb.h |5 +
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net
On 18/08/11 15:03, Andreas Bießmann wrote:
> Dear Dave Aldrige,
>
> Am 18.08.2011 15:32, schrieb Dave Aldridge:
>> The Cadence GEM is based on the MACB Ethernet controller but has a few
>> small changes with regards to register and bitfield placement. This
>> patch de
If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
mapped access will be used to read/write the uart registers.
This is especially useful for SoC devices that implement 16550
compatible uarts but that have peripheral access width constraints.
Signed-off-by: Dave Aldridge
---
Changes for
If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
mapped access will be used to read/write the uart registers.
This is especially useful for SoC devices that implement 16550
compatible uarts but that have peripheral access width constraints.
Signed-off-by: Dave Aldridge
---
Changes for
Hi Tabi Timur-B04825
On 01/09/11 16:39, Tabi Timur-B04825 wrote:
> On Thu, Sep 1, 2011 at 6:40 AM, Dave Aldridge wrote:
>
>> #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE
>> == 0)
>> #error "Please define NS16550 regis
If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
mapped access will be used to read/write the uart registers.
This is especially useful for SoC devices that implement 16550
compatible uarts but that have peripheral access width constraints.
Signed-off-by: Dave Aldridge
---
Changes for
Hi Wolfgang
On 07/09/11 22:22, Wolfgang Denk wrote:
> Dear Dave Aldridge,
>
> In message <1314877212-31552-1-git-send-email-fovs...@gmail.com> you wrote:
>> If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
>> mapped access will be used to read/write the ua
Hi Wolfgang
On 07/09/11 22:36, Wolfgang Denk wrote:
> Dear Dave Aldridge,
>
> In message <1314953234-3977-1-git-send-email-fovs...@gmail.com> you wrote:
>> If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
>> mapped access will be used to read/write the uart
Hi Detlev
On 09/09/11 13:09, Detlev Zundel wrote:
> Hi,
>
>> Dear Dave Aldridge,
>>
>> In message <1314877212-31552-1-git-send-email-fovs...@gmail.com> you wrote:
>>> If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
>>> mapped acce
register base register
locations in GEM.
Signed-off-by: Dave Aldridge
---
Changes for v2:
- Cleaned up issues reported by checkpatch
drivers/net/macb.c | 18 +++-
drivers/net/macb.h | 55
2 files changed, 67 insertions(+), 6
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on the
device type.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 63 ++--
drivers/net/macb.h | 12 ++
2
GEM has configurable receive buffer sizes so requires this to be
programmed up.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 19 +++
drivers/net/macb.h |5 +
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net
Some GEM implementations may support DMA bus widths up to 128 bits.
We can get the maximum supported DMA bus width from the design
configuration register so use that to program the device up.
Signed-off-by: Dave Aldridge
---
drivers/net/macb.c | 25 +
drivers/net
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