On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote:
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARC
On 07/04/2014 04:43 AM, Xiubo Li-B47053 wrote:
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CON
reg |= ns_dev[i].val;
+ out_be32(csu_csl, reg);
+ }
}
int board_late_init(void)
@@ -483,7 +580,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR);
scsi_scan(1);
- enable_ifc_ns_read_access();
+ enable_devices_ns_access();
return
On 07/03/2014 12:51 PM, Xiubo Li wrote:
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address f
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Can you give an example?
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li
---
arch/arm/cpu/ar
On 07/03/2014 12:51 PM, Xiubo Li wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence u
On 05/30/2014 10:22 AM, Alison Wang wrote:
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that ha
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