Hi Simon,
2015-04-17 18:33 GMT+02:00 Simon Glass s...@chromium.org:
+Tom
Hi Franck,
On 4 March 2015 at 13:07, franck.jull...@gmail.com wrote:
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look
2015-03-05 14:52 GMT+01:00 Marek Vasut ma...@denx.de:
On Wednesday, March 04, 2015 at 09:07:00 PM, franck.jull...@gmail.com wrote:
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available interface.
Signed-off-by: Franck Jullien franck.jull...@gmail.com
---
v2: create a new function to improve indentation
v3: more
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available interface.
Signed-off-by: Franck Jullien franck.jull...@gmail.com
---
common/usb_storage.c | 32 +---
1
2015-03-03 23:28 GMT+01:00 Marek Vasut ma...@denx.de:
On Tuesday, March 03, 2015 at 10:17:11 PM, franck.jull...@gmail.com wrote:
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available
From: Franck Jullien franck.jull...@gmail.com
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available interface.
Signed-off-by: Franck Jullien franck.jull...@gmail.com
---
v2: create a new function to improve indentation
common
address. If yes, there are copied to address 0 (or
to the exception vector base address if register EVBAR is
present).
Then, the .text section is relocated from its current location
to the RAM.
Signed-off-by: Franck Jullien franck.jull...@gmail.com
---
arch/openrisc/cpu/start.S | 55
The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.
Signed-off-by: Franck Jullien franck.jull...@gmail.com
---
arch/openrisc/include/asm/spr-defs.h | 13
2014-02-13 1:56 GMT+01:00 Rommel G Custodio sessyargc+u-b...@gmail.com:
Dear Franck Jullien,
Franck Jullien franck.jullien at gmail.com writes:
Hi,
I'd like to know if I have understood it correctly.
When first time booting from NOR, the RCW and PBI must be written
using the JTAG
Hi,
I'd like to know if I have understood it correctly.
When first time booting from NOR, the RCW and PBI must be written
using the JTAG. The last instruction of the PBI must be a jump
(0x13_8080) to the user's code (uboot here).
Am I right ?
Best regards,
Franck.
2013/4/25 Wolfgang Denk w...@denx.de
Dear Franck Jullien,
In message
cajfokbwjyrtqnhub5gotxcpob_xneirnoz+b97ksvsy0fcx...@mail.gmail.com you
wrote:
I'm building u-boot from the git master for a powerpc target. I'm using
the P2020RDB_SDCARD configuration.
During the final link I get
Hi,
I'm building u-boot from the git master for a powerpc target. I'm using
the P2020RDB_SDCARD configuration.
During the final link I get: uboot/arch/powerpc/cpu/mpc85xx/start.S:1118:
relocation truncated to fit: R_PPC_REL24 against symbol `_start_cont'
defined in .text section in
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