On 5/11/2022 4:55 PM, Rasmus Villemoes wrote:
> On 11/05/2022 10.53, Gaurav Jain wrote:
>> HW accelerated hash operations are giving incorrect hash output.
>> so add flush and invalidate for input/output hash buffers.
>>
>> Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using
>> h
One of the "dma_addr_t" instances was left out when
converting to "caam_dma_addr_t".
Fixes: 2ff17d2f74c5 ("crypto: fsl: refactor for 32 bit version CAAM support on
ARM64")
Signed-off-by: Horia Geantă
---
drivers/crypto/fsl/jobdesc.c | 2 +-
1 file changed, 1 ins
On 3/25/2021 11:32 AM, Peng Fan (OSS) wrote:
> From: Peng
>
> This patchset is to upstream NXP downstream caam, hab features
I don't think adding yet another caam driver (drivers/crypto/fsl_caam.c)
is a good idea.
Instead existing driver (drivers/crypto/fsl/*) should be extended / modified.
> O
t;
> Just remove it for older SoCs, where the module is indeed completely
> disabled on non-E parts.
>
> Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
Thanks,
Horia
On 8/10/2020 5:54 PM, Michael Walle wrote:
> On all newer Layerscape SoCs, the crypto module is just partially
> disabled on non-E parts. Thus it doesn't make sense to completely remove
> the node. Linux will figure out what is there and what is not.
>
Could add a clarification here, saying "parti
On 6/19/2020 10:02 PM, Michael Walle wrote:
> Am 2020-06-19 18:54, schrieb Horia Geantă:
>> On 6/19/2020 7:37 PM, Horia Geanta wrote:
>>> On 6/17/2020 11:48 PM, Michael Walle wrote:
>>>> Am 2020-06-17 21:15, schrieb Horia Geantă:
>>>>
On 6/19/2020 7:37 PM, Horia Geanta wrote:
> On 6/17/2020 11:48 PM, Michael Walle wrote:
>> Am 2020-06-17 21:15, schrieb Horia Geantă:
>>> On 6/4/2020 6:48 PM, Michael Walle wrote:
>>>> +
>>>> + desc = memalign(ARCH_DMA_MINALIGN, desc_size);
>>
On 6/17/2020 11:48 PM, Michael Walle wrote:
> Am 2020-06-17 21:15, schrieb Horia Geantă:
>> On 6/4/2020 6:48 PM, Michael Walle wrote:
>>> +
>>> + desc = memalign(ARCH_DMA_MINALIGN, desc_size);
>>> + if (!desc) {
>>> + debug(
On 6/4/2020 6:48 PM, Michael Walle wrote:
> +static int caam_rng_read(struct udevice *dev, void *data, size_t len)
> +{
> + struct caam_rng_platdata *pdata = dev_get_platdata(dev);
> + u8 *buffer = data;
> + size_t size;
> + int ret;
> +
> + while (len) {
> + ret = c
On 6/4/2020 6:48 PM, Michael Walle wrote:
> +static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> +{
> + u32 *desc;
> + int sh_idx, ret = 0;
> + int desc_size = sizeof(u32) * 3;
As you mentioned, descriptor size should be sizeof(u32) * 2.
> +
> + desc = memalign(ARCH_D
On 6/4/2020 6:47 PM, Michael Walle wrote:
> The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a
> POR. Otherwise the RNG4 will throw an error.
>
> Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
Did you meet this problem in practice?
Horia
DR3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
> SEC0: RNG instantiated
> WDT: Started with servicing (60s timeout)
>
> Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
Thanks,
Horia
On 6/3/2020 11:09 PM, Michael Walle wrote:
> [+ Horia]
>
> Am 2020-06-02 17:09, schrieb Michael Walle:
>> At least on the LS1028A the crypto module is always there, but has some
>> functions disabled on non-E parts. Thus it doesn't make sense to
>> completely remove the node. Linux will figure out
On 6/4/2020 5:31 AM, Heinrich Schuchardt wrote:
> On 6/3/20 12:05 AM, Michael Walle wrote:
>> Register the random number generator with the rng subsystem in u-boot.
>> This way it can be used by EFI as well as for the 'rng' command.
>>
>> Signed-off-by: Michael Walle
>> ---
>> drivers/crypto/fsl/
On 6/3/2020 9:25 PM, Michael Walle wrote:
> Hi Horia, Hi Heinrich,
>
> thanks for reviewing.
>
> Am 2020-06-03 19:35, schrieb Heinrich Schuchardt:
>> On 6/3/20 6:50 PM, Horia Geantă wrote:
>>> On 6/3/2020 1:06 AM, Michael Walle wrote:
>>>> Registe
On 6/3/2020 1:06 AM, Michael Walle wrote:
> Since Era 10, the version registers changed. Add the version registers
> and use them on newer modules.
>
> Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
Thanks,
Horia
On 6/3/2020 1:06 AM, Michael Walle wrote:
> We need the era in other modules, too. For example, to get the RNG
> version.
>
> Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
Thanks,
Horia
On 6/3/2020 1:06 AM, Michael Walle wrote:
> @@ -657,7 +657,7 @@ int sec_init_idx(uint8_t sec_idx)
> printf("SEC%u: RNG instantiation failed\n", sec_idx);
> return -1;
> }
> - printf("SEC%u: RNG instantiated\n", sec_idx);
> +
On 6/3/2020 1:06 AM, Michael Walle wrote:
> Register the random number generator with the rng subsystem in u-boot.
> This way it can be used by EFI as well as for the 'rng' command.
>
I am trying to understand what's expected from UCLASS_RNG...
UEFI spec mentions:
<>
lib/efi_loader/efi_rng.c use
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă
Reviewed-by: Zhengxiong Jin
---
v2 - moved initialization in arch_cpu_init (instead of board_early_init_f)
On 10/14/2015 11:54 PM, York Sun wrote:
>
>
> On 09/16/2015 03:22 AM, Horia Geantă wrote:
>> Enable snooping for CAAM read & write transactions by
>> programming the SCFG snoop configuration register:
>> SCFG_SNPCNFGCR[SECRDSNP]
>> SCFG_SNPCNFGCR[SECWRS
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă
Reviewed-by: Zhengxiong Jin
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
board/frees
Use fdt_setprop_u32() instead of fdt_setprop().
Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă
Reviewed-by: Mingkai Hu
---
drivers/crypto/fsl/sec.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/crypto/f
Signed-off-by: Horia Geantă
---
drivers/crypto/fsl/sec.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
index b25b1a4052d2..0940faf768cc 100644
--- a/drivers/crypto/fsl/sec.c
+++ b/drivers/crypto/fsl/sec.c
U (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă
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