Re: [U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA

Am 20.12.2017 um 10:35 schrieb Marek Vasut: > On 12/20/2017 12:29 AM, Jan Siegmund wrote: >> Am 18.12.2017 um 22:05 schrieb Marek Vasut: >>> On 12/18/2017 09:44 PM, Jan Siegmund wrote: >> >> Hi Marek, > > Hi, > Hi Marek, >>>> Hi all, >>&

Re: [U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA

Am 18.12.2017 um 22:05 schrieb Marek Vasut: > On 12/18/2017 09:44 PM, Jan Siegmund wrote: Hi Marek, >> Hi all, > > Hi, > >> Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. >> Is is possible to configure the the interface in U-

[U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA

Hi all, Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL, without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers on

Re: [U-Boot] Linux hang

Am 08.12.2017 um 14:52 schrieb Anatolij Gustschin: Hi, On Wed, 6 Dec 2017 17:02:07 + Siegmund, Jan jan.siegmu...@hm.edu wrote: Hi all, does anybody have an idea for the following problem. * FPGA is programmed using an overlay * FPGA writes to SDRAM via the FPGA2SDRAM-bridge * Linux hangs

Re: [U-Boot] Linux hang

Am 07.12.2017 um 20:19 schrieb Alan Tull: On Thu, Dec 7, 2017 at 5:00 AM, Siegmund, Jan wrote: Hi SIegmund, Hi all, does anybody have an idea for the following problem? * FPGA is programmed using an overlay * FPGA writes to SDRAM via the FPGA2SDRAM-bridge * Linux hangs and the watchdog reset

Re: [U-Boot] Linux hang

Am 07.12.2017 um 15:01 schrieb Goldschmidt Simon: On 2017-12-07 12:01, Siegmund, Jan wrote: Hi all, does anybody have an idea for the following problem? * FPGA is programmed using an overlay * FPGA writes to SDRAM via the FPGA2SDRAM-bridge * Linux hangs and the watchdog resets the board (the FP