[PATCH v4 1/1] arch: arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim --- Changes v3 -> v4: - Update defined to is_enabled Changes v2 -> v3: - Added FPG

[PATCH v4 0/1] Agilex5 enablement

V1: https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.loon@intel.com/ V2: Fixed Git auto-merge causing misalignment of code and insert/delete V3: Added 240G FPGA DDR region V4: Update defined to is_enabled Jit Loon Lim (1): arch: arm: Agilex5 enablement arch/arm

[PATCH v3 v3 1/1] arch: arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim Changes v2 -> v3: - Added FPGA 240G DDR region Changes v1 -> v2: - fixed git auto

[PATCH v3 0/1] Agilex5 enablement

V1: https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.loon@intel.com/ V2: Fixed Git auto-merge causing misalignment of code and insert/delete V3: Added 240G FPGA DDR region Jit Loon Lim (1): arch: arm: Agilex5 enablement arch/arm/Kconfig

[RESEND v2 1/1] arch: arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim --- Changes v1 -> v2: - fixed git auto merge issue --- arch/arm/Kcon

[RESEND v2 0/1] Agilex5 enablement

V1: https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.loon@intel.com/ V2: Fixed Git auto-merge causing misalignment of code and insert/delete Jit Loon Lim (1): arch: arm: Agilex5 enablement arch/arm/Kconfig | 4 +- arch/arm/dts

[PATCH v2 1/1] arch:arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim --- Changes v1 -> v2: - fixed git auto merge issue --- arch/arm/Kcon

[PATCH v2 0/1] Agilex5 enablement

V1: https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.loon@intel.com/ V2: Fixed Git auto-merge causing misalignment of code and insert/delete Jit Loon Lim (1): arch:arm: Agilex5 enablement arch/arm/Kconfig | 13 +- arch/arm/dts

[PATCH v1 1/1] arch:arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim --- arch/arm/Kconfig | 9 +- arch/arm/dts/Makefile

[PATCH v1] doc: Add the link for the documentation of the .its

Provide the link for the .its related documentation for Arria10. Signed-off-by: Jit Loon Lim --- doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree

[PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash

ash device. Signed-off-by: Jit Loon Lim --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ca46330bb..1b2e88cd26 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c

[PATCH v1] drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash

From: Teik Heng Chong Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong --- drivers/mtd/spi/spi-nor-ids.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c

[PATCH v1] HSD #18028953892: usb: xhci-dwc3: Fix USB3.1 controller register access in reset state

From: Teik Heng Chong The controller registers should not be accessed while the controller's vcc_reset_n is asserted. Signed-off-by: Teik Heng Chong --- drivers/usb/host/xhci-dwc3.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-dwc3.c

[PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL

From: Kah Jing Lee Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL. Signed-off-by: Kah Jing Lee --- arch/arm/cpu/armv8/cache_v8.c | 20

[PATCH v1] arm: socfpga: agilex5: Define MMU mapping region for FPGA

From: Sin Hui Kho Add MMU mapping region for FPGA including 512 MB LW HPS2FPGA and 1GB HPS2FPGA. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/mmu-arm64_s10.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c

[PATCH v1] arch: arm: dts: Enable APB Timer for agilex5

From: Dinesh Maniyam Enable APB Timer driver model. Signed-off-by: Dinesh Maniyam --- arch/arm/dts/socfpga_agilex5_socdk.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index

[PATCH v1 17/17] tools: binman: update binman tool for agilex5

From: Sieu Mun Tang This is for new platform enablement for agilex5. Update binman tool for new platform. Signed-off-by: Sieu Mun Tang --- tools/binman/control.py | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/binman/control.py b/tools/binman/control.py

[PATCH v1 12/17] drivers: phy: add combo phy driver for agilex5

This is for new platform enablement for agilex5. Add combo phy driver for new platform. Signed-off-by: Jit Loon Lim --- drivers/phy/cadence/Kconfig| 9 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-combophy.c | 855

[PATCH v1 16/17] includes: add and update configuration for agilex5

This is for new platform enablement for agilex5. Add in new configuration that needed to boot new platform. Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/Kconfig | 55 + configs/socfpga_agilex5_defconfig | 2 + configs/socfpga_agilex5_legacy_defconfig

[PATCH v1 15/17] drivers: watchdog: update watchdog driver for agilex5

This is for new platform enablement for agilex5. Update watchdog timeout timer for new platform. Signed-off-by: Jit Loon Lim --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 646663528a

[PATCH v1 14/17] drivers: sysreset: add system driver for agilex5

This is for new platform enablement for agilex5. Add cold, warm reset logic for new platform. Signed-off-by: Jit Loon Lim --- drivers/sysreset/Kconfig| 7 drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 44

[PATCH v1 13/17] drivers: reset: add reset driver for agilex5

This is for new platform enablement for agilex5. Add reset driver for new platform. Signed-off-by: Jit Loon Lim --- drivers/reset/reset-socfpga.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset

[PATCH v1 11/17] drivers: mmc: add mmc/cadence driver for agilex5

This is for new platform enablement for agilex5. Add mmc and cadence host driver for new platform. Signed-off-by: Jit Loon Lim --- drivers/mmc/mmc.c | 27 +++--- drivers/mmc/sdhci-cadence.c | 164 2 files changed, 160 insertions(+), 31 deletions

[PATCH v1 09/17] drivers: clk: altera: add clock support for agilex5

This is for new platform enablement for agilex5. Add new clock files for new platform.Add Signed-off-by: Jit Loon Lim --- drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex5.c | 736 +++ drivers/clk/altera/clk-agilex5.h | 263 +++ 3 files

[PATCH v1 08/17] drivers: ddr: altera: add ddr support for agilex5

This is for new platform enablement for agilex5. Add new ddr and iossm mailbox files for new platform.Add Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/Makefile| 5 +- drivers/ddr/altera/iossm_mailbox.c | 786 + drivers/ddr/altera/iossm_mailbox.h | 141

[PATCH v1 10/17] drivers: misc: update driver misc for agilex5

This is for new platform enablement for agilex5. Update secure registers, Kconfig and makefile for new platform. Signed-off-by: Jit Loon Lim --- drivers/misc/Kconfig | 9 +++ drivers/misc/Makefile | 1 + drivers/misc/socfpga_secreg.c | 116

[PATCH v1 06/17] configs: add new platform agilex5 defconfig

This is for new platform enablement for agilex5. Add new platform defconfig for new platform. Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex5_defconfig| 123 +++ configs/socfpga_agilex5_legacy_defconfig | 85 2 files changed, 208 insertions

[PATCH v1 07/17] doc: device-tree-bindings: misc: add secreg text file for agilex5

This is for new platform enablement for agilex5. Add new secure register text file for new platform. Signed-off-by: Jit Loon Lim --- .../misc/socfpga_secreg.txt | 397 ++ 1 file changed, 397 insertions(+) create mode 100644 doc/device-tree-bindings/misc

[PATCH v1 05/17] board: intel: add new platform agilex5 socdk

This is for new platform enablement for agilex5. Add new platform socdk and update maintainer list. Signed-off-by: Jit Loon Lim --- board/intel/agilex5-socdk/MAINTAINERS | 8 board/intel/agilex5-socdk/Makefile| 7 +++ board/intel/agilex5-socdk/socfpga.c | 7 +++ 3 files

[PATCH v1 04/17] arch: arm: mach-socfpga: include: mach: add new platform agilex5 mach-socfpga enablement

This is for new platform enablement for agilex5. Add platform related header files to enable new product. Signed-off-by: Jit Loon Lim --- .../include/mach/base_addr_soc64.h| 43 +- .../mach-socfpga/include/mach/clock_manager.h | 5 +- .../include/mach/clock_manager_agilex5.h

[PATCH v1 03/17] arch: arm: mach-socfpga: add new platform agilex5 mach-socfpga enablement

This is for new platform enablement for agilex5. Add platform related files to enable new product. Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/Kconfig | 37 +++ arch/arm/mach-socfpga/Makefile| 69 - arch/arm/mach-socfpga/board.c

[PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5

This is for new platform enablement for agilex5. Add agilex5 dtsi and dts. Update checkpatch error for stratix10. Signed-off-by: Jit Loon Lim --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 + arch/arm/dts

[PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5

This is for new platform enablement for agilex5 Signed-off-by: Jit Loon Lim --- arch/arm/Kconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..8e36456fa8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig

[PATCH v1 00/17] Agilex5 Platform Enablement

Intel Agilex5 is a midrange FPGAs optimized for applications requiring high performance, lower power, and smaller form factors and lower logic densities. U-Boot is one of the bootloader to boot along with ARM trusted Firmware to boot the board up. *** BLURB HERE *** Jit Loon Lim (16): arch

[PATCH] mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl

From: "Lokanathan, Raaj" Add support for reading data/images from this ISSI QSPI flash. Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- drivers/mtd/spi/spi-nor-tiny.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-no

[PATCH] arm: socfpga: Expand the help text for the bridge command.

x 10: bit3: f2sdram0 bit4: f2sdram1 bit5: f2sdram2 Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/misc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de7..0112cfd

[PATCH 2/2] configs: increase CONFIG_SYS_BOOTM_LEN to support kernel > 32MB

From: Kah Jing Lee Increase CONFIG_SYS_BOOTM_LEN to support kernel image from 5.15.lts that is > 32MB Signed-off-by: Kah Jing Lee Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_soc64_commo

[PATCH 1/2] configs: add env. variable to support compressed kernel in qspiboot

From: Kah Jing Lee Fix qspiboot issue which uncompressed kernel(5.16) overflows to rootfs Add 2 env. variables to support compressed kernel in legacy qspiboot: setenv kernel_comp_addr_r 0x900 setenv kernel_comp_size 0x0100 Signed-off-by: Kah Jing Lee Signed-off-by: Jit Loon Lim

[PATCH] Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver

From: "Lokanathan, Raaj" Add the CONFIG_SYS_NAND_SELF_INIT to the Kconfig to follow the changes from mainline. Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- drivers/mtd/nand/raw/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw

[PATCH] spl: fit: nand: fix fit loading on bad blocks

of the sectors concerned. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- common/spl/spl_nand.c | 3 +- drivers/mtd/nand/raw/denali.c | 91 ++- 2 files changed, 92 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_nand.c b/common/spl

[PATCH] mtd: spi-nor-ids: add Macronix flash entry

From: Tien Fong Chee Add Macronix mx25u51245g flash entry, so this can be used on SoCFPGA devices. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b

[PATCH] include: configs: socfpga: Add environment variables for distro boot

From: Yau Wai Gan Added environment variables needed to support distro boot. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 81 +- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/include/configs

[PATCH 3/4] arm: dts: Update NAND MTD partition for Agilex and Stratix 10

From: Sin Hui Kho Change NAND flash MTD partition in device tree after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components. Signed-off-by: Sin Hui Kho Signed-off-by: Jit

[PATCH 1/4] configs: defconfig: Enable UBI and UBIFS for Agilex and Stratix10

From: Sin Hui Kho Enabling configs required for UBI and UBIFS commands. Set environment in a UBI volume. So, remove CONFIG_ENV_IS_IN_NAND as the environment is now in UBI volume. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_nand_atf_defconfig| 11

[PATCH 4/4] arm: socfpga: soc64: Load and boot for NAND flash with UBI and UBIFS in enviroment

From: Sin Hui Kho Load kernel and device tree from UBI volume. Set root file system type for NAND boot as UBIFS located at UBI volume on MTD partition 1 or namely "root". Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 9 +++

[PATCH 2/4] configs: defconfig: Update default NAND MTD partition for Agilex and Stratix 10

From: Sin Hui Kho Change default MTD partition scheme for NAND flash after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components. Signed-off-by: Sin Hui Kho Signed-

[PATCH] arm: socfpga: Export Board ID as U-boot Environment Variable

From: Yau Wai Gan Board ID is exported as environment variable for use to boot Linux FIT configuration. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/misc_soc64.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_soc64.c

[PATCH] arm: socfpga: Enable U-boot FIT Config Name Match with Board ID

From: Yau Wai Gan U-boot FIT configuration shall be selected based on the Board ID that is set. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/board.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-socfpga

[PATCH] arm: socfpga: Add function to get Board ID

From: Yau Wai Gan Board ID is defined in JTAG User Code register. This function retrieves the Board ID and perform validation on it. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/board.c | 39 +++ .../mach-socfpga/include

[PATCH] arm: socfpga: soc64: Add support for board_boot_order()

From: Sin Hui Kho Add board_boot_order() to retrieve the list of boot devices from spl-boot-order property in device tree. This board_boot_order() will use for all Intel SOC64 device for single SPL binary. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga

[PATCH 3/6] arm: dts: socfpga: Copy existing FW & SEC config to DTS

From: Tien Fong Chee Copy existing firewall and secure register settings in source codes to device tree. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_agilex-u-boot.dtsi| 13 ++- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 10 ++ arch/arm/dts

[PATCH 6/6] arm: socfpga: Enhance checking on potential overwrite

. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/misc/socfpga_secreg.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c index a4b297e7f1..0ea30c254b 100644 --- a/drivers/misc/socfpga_secreg.c

[PATCH 4/6] arm: dts: socfpga: Update existing FW & SEC config to DTS

From: Tien Fong Chee Update N5X existing firewall and secure register settings in source codes to device tree. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_n5x-u

[PATCH 2/6] misc: socfpga_secreg: Enable register settings in DTS

Loon Lim --- drivers/misc/Kconfig | 9 drivers/misc/Makefile | 2 + drivers/misc/socfpga_secreg.c | 86 +++ 3 files changed, 97 insertions(+) create mode 100644 drivers/misc/socfpga_secreg.c diff --git a/drivers/misc/Kconfig b/drivers/misc

[PATCH 5/6] arm: socfpga: Switch FW settings from codes to DTS

From: Tien Fong Chee Switching the firewall, and high privilege registers setting in source codes over to device tree implementation. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/Kconfig | 2 ++ arch/arm/mach-socfpga/Makefile

[PATCH 1/6] doc: dtbinding: Add doc for privilege regs settings

From: Tien Fong Chee Add a document to describe firewall and privilege register settings binding information. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- .../misc/socfpga_secreg.txt | 26 +++ 1 file changed, 26 insertions(+) create mode

[PATCH] ddr: altera: n5x: Include DDR4 for the same hardcoding settings

From: Tien Fong Chee Below settings are required for DDR4 to get some DDR chips properly retention entry and exit. Register INIT0 = 0xF87F_80D0 = bits [31-30] = [11] Register PWRCTL = 0xF87F_8030 = bit [5] = 1 Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_n5x.c | 79

[PATCH] configs: socfpga: soc64: Disable CONFIG_SPL_RAW_IMAGE_SUPPORT

is common for all Intel SOC64 devices. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_nand_atf_defconfig | 3 ++- configs

[PATCH 2/5] misc: socfpga_secreg: Enable register settings in DTS

Loon Lim --- drivers/misc/Kconfig | 9 drivers/misc/Makefile | 2 + drivers/misc/socfpga_secreg.c | 86 +++ 3 files changed, 97 insertions(+) create mode 100644 drivers/misc/socfpga_secreg.c diff --git a/drivers/misc/Kconfig b/drivers/misc

[PATCH 5/5] arm: socfpga: Switch FW settings from codes to DTS

From: Tien Fong Chee Switching the firewall, and high privilege registers setting in source codes over to device tree implementation. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/Kconfig | 2 ++ arch/arm/mach-socfpga/Makefile

[PATCH 1/5] doc: dtbinding: Add doc for privilege regs settings

From: Tien Fong Chee Add a document to describe firewall and privilege register settings binding information. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- .../misc/socfpga_secreg.txt | 26 +++ 1 file changed, 26 insertions(+) create mode

[PATCH 3/5] arm: dts: socfpga: Copy existing FW & SEC config to DTS

From: Tien Fong Chee Copy existing firewall and secure register settings in source codes to device tree. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_agilex-u-boot.dtsi| 13 ++- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 10 ++ arch/arm/dts

[PATCH 4/5] arm: dts: socfpga: Update existing FW & SEC config to DTS

From: Tien Fong Chee Update N5X existing firewall and secure register settings in source codes to device tree. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_n5x-u

[PATCH] ddr: altera: n5x: Fixing debug log typo

From: Tien Fong Chee Fixing debug log typo. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index

[PATCH] ddr: altera: n5x: Fixing debug log typo

From: Tien Fong Chee Fixing debug log typo. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index

[PATCH] drivers: fpga: Add FPGA configuration during bootm for Intel SOCFPGA

From: Yau Wai Gan This enable the capability to automatically perform FPGA configuration when booting Linux FIT image via bootm command. The FPGA configuration bitstream shall be packed within the FIT image. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- drivers/fpga/altera.c

[PATCH] ddr: altera: n5x: Ensure 'cal->header.data_len' is validated

y when reading this variable. Adding checking on 'cal->header.data_len' to ensure the value is valid for the sake of good coding practice. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 44 +++--- 1 file changed, 36 i

[PATCH] ddr: altera: n5x: Ensure correct size of result for correct type casting

for the sake of good coding practice. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 72c231b3f1..0e944b7a15 100644

[PATCH] ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set

From: Tien Fong Chee Ensure the PHY calibration data is copied to DDR only when DDR retention is set. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/ddr

[PATCH] ddr: altera: n5x: Return error if invalid DDR type is detected in argument

From: Tien Fong Chee Return error immediately if invalid DDR type is detected in argument so that uninitialized local variables such val and upd_val would not be used. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 3 +++ 1 file changed, 3

[PATCH] arm: socfpga: soc64: Fix with correct header file

From: Tien Fong Chee HSD #18016722456: Includes only required header for mdelay function. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/secure_vab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/secure_vab.c b

[PATCH] ddr: altera: n5x: Checking DDR init hang before reset due to watchdog

From: Tien Fong Chee DDR need to be initialized and running calibration if DDR init hang before reset due to watchdog. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 30 ++ 1 file changed, 22 insertions(+), 8

[PATCH] ddr: altera: n5x: Checking DDR DBE

From: Tien Fong Chee DDR need to be initialized and running calibration if DBE is triggered Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 33 - 1 file changed, 24 insertions(+), 9 deletions(-) diff --git

[PATCH] arm: socfpga: n5x: Update DDR init progress bit

From: Tien Fong Chee The bit[30] of boot scratch cold 8 register is used as DDR init progress tracking by SDM when watchdog is triggered due to ddr init hang, so that SDM can run a clean reset to DDR subsystem. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera

[PATCH] arm: socfpga: Define the usage of boot scratch cold reg 8

From: Tien Fong Chee The boot scratch cold reg 8 is shared between DBE, DDR init progress update and Linux EDAC. This patch defines how the bits are used by respective features above and their macro names used in U-Boot. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim

[PATCH] arm: socfpga: soc64: Add malloc.h

From: Tien Fong Chee HSD #1308580006: Some compilers complaint implicit declaration of malloc function, and some compilers have no this issue. Adding malloc.h to resolve this issue. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/secure_vab.c | 9

[PATCH 2/2] arm: socfpga: soc64: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES

From: Ley Foon Tan HSD #18016042797-2: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES SMC call. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/reset_manager_s10.c | 10 +++--- include/linux/intel-smc.h | 14 ++ 2 files

[PATCH 1/2] arm: socfpga: soc64: Add mask support when enable/disable bridges

: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- .../include/mach/reset_manager_soc64.h| 9 +- arch/arm/mach-socfpga/misc_soc64.c| 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 154 +++--- 3 files ch

[PATCH] arm: socfpga: n5x: Replace with soc64 env settings

From: Tien Fong Chee Only DDR and clock changes in N5X compare with existing SOC64 devices, so a common SOC64 env setting can be used in N5X. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- include/configs/socfpga_n5x_socdk.h | 33 - 1 file changed

[PATCH] ddr: altera: n5x: Add self-refresh support in DDR4

From: Tien Fong Chee Enable self-refresh support in DDR4 for retaining DDR4 content with minimal power when reset is triggered. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- .../include/mach/system_manager_soc64.h | 3 +- drivers/ddr/altera/sdram_n5x.c

[PATCH] arm: dts: n5x: User interface for DDR self-refresh configuration

From: Tien Fong Chee These are interface for users to customize some settings in DDR self-refresh configuration according to their design requirement. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 + 1 file changed

[PATCH] arm: socfpga: n5x: Enables mailbox functionality for QSPI before DDR

From: Tien Fong Chee Enables mailbox functionality for QSPI before initializing DDR, because storing calibration data into QSPI is required when DDR retention is enabled. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/spl_n5x.c | 12 ++-- 1 file

[PATCH] arm: socfpga: Add boolean use_fit to run specific commands when using fit image

ot;. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/board.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7267163222..914a44970d 100644 --- a/arch/arm/mach-socfpga/boa

[PATCH] net: phy: micrel: Get phy node from phy-handle

From: Ley Foon Tan HSD #1509063521: Try to get phy node from "phy-handle" if can't find ethernet-phy subnode. Lastly only use Ethernet node if can't find phy node from ethernet-phy subnode and phy-handle. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- drive

[PATCH] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

From: Yau Wai Gan FPGA configuration encounter failure when the cache is not flushed. Add cache flushing to the memory region that holds the FPGA configuration bitstream. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- drivers/fpga/intel_sdm_mb.c | 6 ++ 1 file changed, 6

[PATCH 1/2] drivers: watchdog: Enhance watchdog support in SPL for Stratix 10 and Agilex

From: Siew Chin Lim Change watchdog default timeout to 10 seconds and enable watchdog before initializing other component (example: DDR). Thus, watchdog need to be fully executed in onchip ram. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/spl_agilex.c

[PATCH 2/2] drivers: watchdog: Enhance watchdog support in SPL for N5X

From: Siew Chin Lim Enable watchdog before initializing other component (example: DDR). Thus, watchdog need to be fully executed in onchip ram. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/spl_n5x.c | 17 ++--- 1 file changed, 10 insertions

[PATCH] arm: socfpga: n5x: Remove invalid configuration for N5X

From: Tien Fong Chee These configurations no longer valid for N5X, remove them. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/Kconfig | 1 - arch/arm/mach-socfpga/Makefile | 11 +++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git

[PATCH] ddr: altera: n5x: Enhance driver to support LPDDR4

From: Tien Fong Chee Enhance driver to common DDR driver for supporting both DDR4 and LPDDR4. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_n5x_socdk-u

[PATCH] ddr: altera: n5x: Remove all codes used for emulation

From: Tien Fong Chee Remove all DDR4 codes used for emulation in preparation to run on n5x device. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers

[PATCH] ddr: altera: n5x: Restructure DDR driver in preparation to support LPDDR4

From: Tien Fong Chee Restructure DDR driver so that driver has the ability to recognize the DDR type by populating DDR handoff from bitstream. This is also in preparation to improve driver for supporting additional LPDDR4. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers

[PATCH 2/2] include: configs: soc64: Update source command format

From: Yau Wai Gan HSD #1509829545-2: U-boot script is in FIT image, this requires to update the source command to supply the FIT subimage name. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 1/2] arm: dts: soc64: Add U-boot script in FIT Image

From: Yau Wai Gan HSD #1509829545-1: Build u-boot script in FIT image format to align with binman usage. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 23 ++ 1 file changed, 23 insertions(+) diff --git a/arch/arm

[PATCH] include: configs: soc64: Disable SPL load U-Boot image using raw method

From: Sin Hui Kho Since u-boot raw image is no longer supported, SPL will not use raw method to load u-boot raw image. This changes is applicable for all Intel SOC64 device for NAND boot. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 3

[PATCH] configs: socfpga: Wrapping up function ID for SMC register access

. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 7edffc3975..170b647826 100644

[PATCH] configs: socfpga: n5x: Enables required configs for DDR retention

From: Tien Fong Chee Enables required configs to support DDR retention. including generic firmware loader for loading backup calibration data, and SHA384 checking. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- configs/socfpga_n5x_atf_defconfig | 5 + configs

[PATCH] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile

file of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/socfpga

[PATCH] configs: defconfig: Boot to OS via FIT Image for N5X

From: Siew Chin Lim Update to boot OS via FIT image from N5X and enable FIT signature check via crc32 algorithm. And, remove CONFIGs for emulation only. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- configs/socfpga_n5x_atf_defconfig | 4 +++- configs/socfpga_n5x_vab_defconfig

[PATCH] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function

, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_nand_atf_defconfig| 2 +- configs/socfpga_agilex_qspi_atf_defconfig| 2 +- configs

[PATCH] configs: defconfig: Load OS via FIT image in QSPI ATF boot for Stratix 10 and Agilex

From: Siew Chin Lim Update to load OS via FIT image in Stratix 10 and Agilex QSPI ATF boot flow. And, enable FIT signature checking with crc32 algorithm. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_qspi_atf_defconfig| 6 +- configs

  1   2   >