[U-Boot] [PATCH 2/2] board: advantech: dms-ba16:: add the Q7 DualLite support

Change the dms-ba16 configurations to support both Q7 Dual/Quad and DualLite modules Add the DDR3L parameters support for the DualLite Signed-off-by: Ken Lin --- arch/arm/mach-imx/mx6/Kconfig | 1 - board/advantech/dms-ba16/Kconfig| 7 +++ board/advantech/dms-ba16

[U-Boot] [PATCH 1/2] board: advantech: dms-ba16: GBE MAC addr support in kernel bootargs

Add configurable support for loading the GBE MAC from the Q7 SPI-NOR and add it to the kernel bootargs. Signed-off-by: Ken Lin --- board/advantech/dms-ba16/Kconfig | 3 +++ board/advantech/dms-ba16/dms-ba16.c | 19 +++ include/configs/advantech_dms-ba16.h | 13

[U-Boot] [PATCH] arm: imx: Add Winbond SPI-NOR support for Advantech DMS-BA16 board

Windbond's been in the AVL list and need to enable the support Signed-off-by: Ken Lin --- configs/dms-ba16-1g_defconfig | 1 + configs/dms-ba16_defconfig| 1 + 2 files changed, 2 insertions(+) diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index 40b31

[U-Boot] [PATCH 2/4] board: advantech: dms-ba16: add the PMIC configuration support

Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue Signed-off-by: Ken Lin --- board/advantech/dms-ba16/dms-ba16.c | 51 + 1 file changed, 51 insertions(+) diff --git a/board/advantech/dms-ba16/dms-ba16.c b

[U-Boot] [PATCH 4/4] board: advantech: dms-ba16: apply the proper register setting to fix the voltage peak issue

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Signed-off-by: Ken Lin --- board/advantech/dms-ba16/dms-ba16.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[U-Boot] [PATCH 3/4] board: advantech: dms-ba16: fix AR8033 reset timing issue

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet Signed-off-by: Ken Lin --- board/advantech/dms-ba16/dms-ba16.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/advantech/dms-ba16

[U-Boot] [PATCH 1/4] board: advantech: dms-ba16: Add the configuration options for display initialization

Add the configuration options for display initialization in case we need to do the display initialization in kernel to support different timing settings Signed-off-by: Ken Lin --- board/advantech/dms-ba16/dms-ba16.c | 3 +++ include/configs/advantech_dms-ba16.h | 2 ++ 2 files changed, 5

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Signed-off-by: Ken Lin --- Changes from v1 - New commit message board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2

[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet Signed-off-by: Ken Lin --- Changes from v1 - Fix the missing Signed-off-by issue board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Signed-off-by: Ken Lin --- Changes from v1 - New commit message board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2

[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet Signed-off-by: Ken Lin --- Changes from v1 - Fix the missing Signed-off-by issue board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion

[U-Boot] [RFC v2] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

Apply the previous setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Tested on Advantech DMS-BA16 board Tested-by: Ken Lin Signed-off-by: Ken Lin --- drivers/net/phy/atheros.c | 8 1

[U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

Apply the previous setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Tested on Advantech DMS-BA16 board Tested-by: Ken Lin Signed-off-by: Ken Lin --- drivers/net/phy/atheros.c | 8 1