[U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

Hi Joe and Mugunthan, We encountered the voltage peak issue while doing the IEEE PHY conformance test, which has to do with the AR8033 register (SetDes Test and System Mode Control) setting in u-boot. In your commit change info, you tried to enable tx clock delay by setting bit 8 to 1 (filling

Re: [U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

> -Original Message- > From: Sekhar Nori [mailto:nsek...@ti.com] > Sent: Tuesday, January 17, 2017 3:23 AM > To: Ken.Lin; joe.hershber...@ni.com > Cc: Peter.Stretz; mugunthan...@ti.com; Peter.Chiang; Chiming.Lee; u- > b...@lists.denx.de; albert.u.ub...@aribaud.net; w...

Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

> -Original Message- > From: Sekhar Nori [mailto:nsek...@ti.com] > Sent: Thursday, February 2, 2017 9:44 PM > To: ken ; sba...@denx.de > Cc: u-boot@lists.denx.de; martin.donne...@ge.com; Ken.Lin; Peter.Chiang; > Peter.Stretz; akshay.b...@timesys.com; joe.hershber...@ni.

Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

> -Original Message- > From: Sekhar Nori [mailto:nsek...@ti.com] > Sent: Monday, February 6, 2017 12:53 AM > To: Ken.Lin; ken ; sba...@denx.de > Cc: u-boot@lists.denx.de; martin.donne...@ge.com; Peter.Chiang; Peter.Stretz; > akshay.b...@timesys.com; joe.hershber...@ni.