Dear Dirk,
Ah, I was busy yesterday. Well, I can write the message now.
> I wonder if there is any patch missing here? Is it correct that this series
> stops after 2 patches? Shouldn't there be at least something added to board
> directory? And I miss a config file to be able to compile this stuf
Signed-off-by: HeungJun, Kim
---
This patch is the new processor - S5PC100's SoC code & headers.
This patch consists of 2 files.
The First file is to create the new SoC code related with S5PC100
application processor.
It's located in ther cpu/arm_cortesa8/s5pc100.
The Second file is to create
Signed-off-by: HeungJun, Kim
---
This patch is the new processor - S5PC100's SoC code & headers.
This patch consists of 2 files.
The First file is to create the new SoC code related with S5PC100
application processor.
It's located in ther cpu/arm_cortesa8/s5pc100.
The Second file is to create
CC: Dirk Behme
Signed-off-by: HeungJun, Kim
---
The omap3 L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c. Because, it must be CortexA8 ARCH generic
code below the cpu/arm_cortexa8.
This patches fixes the First issue in the following
http
Dear Wolfgang Denk,
I have a question about git-format-patch usage.
I generated the patch using git-format-patch.
The my usage is the following :
1. pull latest git repo.
2. change the code
3. # git commit -a -s
4. insert commit & any other things.
5. # git-format-patch -1
So, I get patch. But,
/pipermail/u-boot/2009-June/053533.html
It's my fault that u don't understand my words :)
BTW, Very thanks to review.
Best Regards,
riverful
2009/6/1 Kim, Heung Jun :
> CC: Dirk Behme
> Signed-off-by: HeungJun, Kim
>
> ---
>
> The L2 cache enable/disable function in the
CC: Dirk Behme
Signed-off-by: HeungJun, Kim
---
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed
mments.
Is it right or something like?
BTW, Thanks one more :)
Best Regards,
riverful
2009/6/2 Kim Phillips :
> On Mon, 1 Jun 2009 19:14:49 +0900
> "Kim, Heung Jun" wrote:
>
>> CC: Dirk Behme
>> Signed-off-by: HeungJun, Kim
>>
>> ---
>>
>>
CC: Dirk Behme
Signed-off-by: HeungJun, Kim
---
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
This patches fixes the First issue in the following
http://lists.denx.de/pipermail/u-boot/2009-May/053433.html
The Second issue is fixed
30 May , Dirk Behme wrote:
>>> Reset is SoC specific and not ARM Cortex A8 generic. Move it from generic
>>> code to OMAP3 SoC specific file.
>>>
>>> CC: "Kim, Heung Jun"
>>> Signed-off-by: Dirk Behme
>>>
>>> ---
>>
Dear Jean,
I miss mail title sorry. :)
=
Dear Jean,
I made new patch about L2 cane enable/disable function.
The related thread is here.
http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html
I fixed title issue & apart header.
Thanks to read :)
Best Regards,
riverful
Dear Jean,
I made new patch about L2 cane enable/disable function.
The related thread is here.
http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html
I fixed title issue & apart header.
Thanks to read :)
Best Regards,
riverful
=
omap3 L2 cache enable/disable function moved from cpu
The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.
Signed-off-by: HeungJun, Kim
---
cpu/arm_cortexa8/cpu.c | 65 +
cpu/arm_cortexa8/omap3/Makefile|2 +-
cpu/arm_cortexa8/omap3/board.c
Thanks to point. Dirk.
And call me "riverful" next time, plz :)
> Kim mentioned that he shuffles around the code due to compile errors while
> adding his new code. So we have to see if we can stay with the current
> implementation or have to change something.
Yes. I shuffles around a little now.
Hi? I'm about to suggest one more thing related to "change cpu.c under
cpu/arm_cortexa8 dir to common code.".
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
It's the common feature all over the arm core, not only arm cortex A8.
The common cache function is defined in the lib_arm/cache-cp15.c as you
First of all, thanks for reading this to Dirk, Jean-Christophe.
>> Anyway, yes, from functionality point of view I agree this patch. OMAP3 was
>> the first Cortex A8 device. So it was more or less expected that while
>> adding additional ones we have to re-arrange some stuff. Being the first
>>
Sorry about wrong Signed-off-by.
Signed-off-by: riverful.kim
Regards,
Kim, HeungJun
2009/5/27 Kim, Heung Jun :
> The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
> The part of cache in cpu.c is moved in the omap3/board.c,
> because the functions about controlling cache se
The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
The part of cache in cpu.c is moved in the omap3/board.c,
because the functions about controlling cache seems to be different with a lot
of processors.
Signed-off-by: root
---
cpu/arm_cortexa8/cpu.c | 55 +-
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