Set upper 32bit address for DMA descriptors and buffer address to support
64-bit addressing.
Signed-off-by: Ley Foon Tan
---
drivers/net/dwc_eth_qos.c | 36
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers
s => socfpga_n5x_socdk.dts} | 59 +++
> 4 files changed, 275 insertions(+), 39 deletions(-)
> create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (82%)
>
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
On Mon, Jul 12, 2021 at 5:50 PM Siew Chin Lim
wrote:
>
> Add device tree for N5X.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
>
> ---
> v4:
> - Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
> to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
>
>
/altera/sdram_soc64.h | 1 +
> 6 files changed, 2386 insertions(+), 2 deletions(-)
> create mode 100644 drivers/ddr/altera/sdram_n5x.c
>
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
On Sun, Jun 13, 2021 at 4:49 PM Siew Chin Lim
wrote:
>
> Add device tree for N5X.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
>
> ---
> v3:
> - Update comment for memory example code
> - Move all common dts settings for N5X from
> socfpga_n5x_socdk.dts to
-n5x.h | 84 +++
> 3 files changed, 221 insertions(+)
> create mode 100644 drivers/clk/altera/clk-mem-n5x.c
> create mode 100644 drivers/clk/altera/clk-mem-n5x.h
>
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
ltera/clk-n5x.h | 217
> include/dt-bindings/clock/n5x-clock.h | 71
> 4 files changed, 779 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/altera/clk-n5x.c
> create mode 100644 drivers/clk/altera/clk-n5x.h
> create mode 100644 include/d
mach/handoff_soc64.h | 38 -
> arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
> arch/arm/mach-socfpga/wrap_handoff_soc64.c| 132 +-
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
I'm no longer work in Intel, change Intel SoCFPGA co-maintainer to
Tien Fong Chee.
Signed-off-by: Ley Foon Tan
---
v2: Fixed typo "Maintainted" to "Maintained".
---
MAINTAINERS| 4 ++--
doc/git-mailrc | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff -
On Fri, Jul 2, 2021 at 1:40 AM Sean Anderson wrote:
>
>
>
> On 7/1/21 12:01 PM, Ley Foon Tan wrote:
> > I'm no longer work in Intel, change Intel SoCFPGA co-maintainer to
> > Tien Fong Chee.
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> >
I'm no longer work in Intel, change Intel SoCFPGA co-maintainer to
Tien Fong Chee.
Signed-off-by: Ley Foon Tan
---
MAINTAINERS| 2 +-
doc/git-mailrc | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 86ff5e04a6..4997ac97a8 100644
4_common.h
> @@ -82,7 +82,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> * Environment variable
> */
>
> -#ifdef CONFIG_FIT
> +#if IS_ENABLED(CONFIG_SPL_ATF)
> #define CONFIG_BOOTFILE "kernel.itb"
> #else
> #define CONFIG_BOOTFILE "Image"
> --
> 2.19.0
>
Reviewed-by: Ley Foon Tan
On Fri, Apr 30, 2021 at 3:41 PM Siew Chin Lim
wrote:
>
> The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
> memory reset manager and memory clock manager.
>
> Configuration settings of controller, PHY and memory reset manager
> is come from DDR handoff data in bitstream, which
1
> 5 files changed, 61 insertions(+), 25 deletions(-)
> copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig}
> (87%)
> copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (82%)
> copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig}
> (87%)
>
Reviewed-by: Ley Foon Tan
On Fri, May 28, 2021 at 4:34 PM Ley Foon Tan wrote:
>
> On Fri, Apr 30, 2021 at 3:41 PM Siew Chin Lim
> wrote:
> >
> > Add device tree for N5X.
> >
> > Signed-off-by: Siew Chin Lim
> > Signed-off-by: Tien Fong Chee
> >
> > --
On Fri, Apr 30, 2021 at 3:41 PM Siew Chin Lim
wrote:
>
> Add device tree for N5X.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
>
> ---
> v2:
> - Remove socfpga_n5x.dtsi
> - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
> n5x data accordingly.
> ---
>
> --- a/arch/arm/mach-socfpga/spl_agilex.c
> +++ b/arch/arm/mach-socfpga/spl_n5x.c
> @@ -1,27 +1,26 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
Reviewed-by: Ley Foon Tan
puts("in power of two!\n");
> + hang();
> + }
> }
> +
> total_ram_check += ram_check;
> ram_check = 0;
> }
> --
> 2.19.0
>
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
On Fri, Apr 30, 2021 at 3:40 PM Siew Chin Lim
wrote:
>
> Add memory clock manager driver for N5X. Provides memory clock
> initialization and enable functions.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2:
> - common.h need to be included before clock_manager.h
> - For consistency, use small
On Fri, Apr 30, 2021 at 3:39 PM Siew Chin Lim
wrote:
>
> Add clock manager driver for N5X. Provides clock initialization
> and get_rate functions.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2:
> - common.h need to be included before clock_manager.h
> - Remove unnecessary comment : write 1 to
On Fri, Apr 30, 2021 at 3:39 PM Siew Chin Lim
wrote:
>
> N5X support both HPS handoff data and DDR handoff data.
> Existing HPS handoff functions are restructured to support both existing
> devices and N5X device.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
>
> ---
> v2:
>
e
> 'linux_qspi_enable' correctly in ATF boot flow
> ---
> arch/arm/mach-socfpga/board.c | 17 +
> configs/socfpga_agilex_atf_defconfig| 2 +-
> configs/socfpga_stratix10_atf_defconfig | 2 +-
> 3 files changed, 11 insertions(+), 10 deletions(-)
>
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
My mail address doesn't work any longer, change to gmail.
Signed-off-by: Ley Foon Tan
---
MAINTAINERS| 2 +-
doc/git-mailrc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 20092cb36740..fc1529ff3c1f 100644
--- a/MAINTAINERS
+++ b
Add FIFO mode support for SoCFPGA dwmmc, read "fifo-mode" property from DT.
Signed-off-by: Ley Foon Tan
---
drivers/mmc/socfpga_dw_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index d6d2d5721411..be3d8bfb3
If can't find ethernet-phy subnode, try to get phy node from "phy-handle".
Lastly, only use Ethernet node if can't find phy node from ethernet-phy
subnode and phy-handle.
Signed-off-by: Ley Foon Tan
---
drivers/net/phy/micrel_ksz90x1.c | 11 +--
1 file changed, 9 insert
So, it doesn't clear the next pending
interrupts unintentionally after read from FIFO.
Signed-off-by: Ley Foon Tan
---
drivers/mmc/dw_mmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7c8a312fa71a..a949dad57402 100
flow.
Signed-off-by: Ley Foon Tan
---
Makefile | 5 -
tools/socfpgaimage.c | 41 -
2 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/Makefile b/Makefile
index 679e4a603a28..e7ff15d419c4 100644
--- a/Makefile
+++ b/Makefile
Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to
size of OCRAM.
This is preparation for image padding change in socfpgaimage.
Signed-off-by: Ley Foon Tan
---
include/configs/socfpga_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs
014
Header checksum : 0x0237
Signed-off-by: Ley Foon Tan
---
tools/socfpgaimage.c | 45 +---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
index 3ba3c93af1bd..5808b383e9cb 100644
--- a/tools/socf
On Fri, Jul 17, 2020 at 9:29 PM Tom Rini wrote:
>
> On Wed, Jun 24, 2020 at 04:34:03PM +0800, Ley Foon Tan wrote:
>
> > From: Chin Liang See
> >
> > This fixes CVE-2016-9841. Changes integrated from [1], with changes
> > make for Uboot code base.
> >
>
/ug/ug_soc_eds.pdf
Signed-off-by: Ley Foon Tan
---
tools/socfpgaimage.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
index 6dfd64e31dd5..f71b3d59ddcb 100644
--- a/tools/socfpgaimage.c
+++ b/to
Add param entry point (ep) support for Arria 10 header. User can pass in
'e' option to mkimage to set the entry point. This is an optional option.
If not specified, default is 0x14.
Signed-off-by: Ley Foon Tan
---
tools/socfpgaimage.c | 21 +
1 file changed, 13 insertions
When load the last block, the "len" might not be a block size. This cause
loading the incorrect last block data.
The fix change "len" to tftp_block_size and minus one tftp_block_size
for offset calculation.
Use same offset calculation formula as in store_block().
Signed-
e fix pass in tftp_cur_block to store_block() and minus the
tftp_block_size when do the offset calculation.
Signed-off-by: Ley Foon Tan
---
net/tftp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/net/tftp.c b/net/tftp.c
index 9ca7db256112..6e68a427d4cf 100644
--- a/net/tftp.c
a large file when block
number is greater than 16-bit (0x).
Signed-off-by: Ley Foon Tan
---
net/tftp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/tftp.c b/net/tftp.c
index c05b7b5532b9..9ca7db256112 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -478,6 +478,7 @@ static void
This patch series fix the tftp block number rollover bugs
when sending and receiving large file (block number
greater than 16-bit).
Tested receiving and sending large file with block
number greater than 0x, verified content
is 100% matched. Tested file size 128MB and 256MB.
Ley Foon Tan (3
From: Dalon Westergreen
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.
Signed-off-by: Dalon Westergreen
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/qts
Westergreen (2):
arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Ley Foon Tan (1):
arm: dts: socfpga: arria10: Move to use generic handoff dtsi
arch/arm/dts/socfpga_arria10-handoff.dtsi | 291
From: Dalon Westergreen
Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.
Signed-off-by: Dalon Westergreen
Signed-off-by: Ley Foon Tan
---
.../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 ++
1 file changed, 305
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-handoff.dtsi | 291
.../socfpga_arria10_socdk_sdmmc-u
Bacrau
Signed-off-by: Ley Foon Tan
---
v2:
- Added "Tested-by" in commit message.
---
drivers/mtd/nand/raw/denali_dt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
index 2728e8098faa..75ad15b0758c 100644
--- a/d
Signed-off-by: Radu Bacrau
Signed-off-by: Ley Foon Tan
---
v2:
- Added "Tested-by" in commit message.
- Restore "bootstrap process" in comment.
---
drivers/mtd/nand/raw/denali.c| 11 +++
drivers/mtd/nand/raw/denali.h| 1 +
drivers/mtd/nand/raw/denali_dt.c | 11
Signed-off-by: Ley Foon Tan
---
drivers/mtd/nand/raw/denali.c| 11 +++
drivers/mtd/nand/raw/denali.h| 1 +
drivers/mtd/nand/raw/denali_dt.c | 10 +++---
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
Always put the controller in reset, then take it out of reset.
This is to make sure controller always in reset state in both SPL and
proper Uboot.
This is preparation for the next patch to poll for reset completion
(rst_comp) bit after reset.
Signed-off-by: Radu Bacrau
Signed-off-by: Ley Foon
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.
This fixes write to invalid address.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/misc_s10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b
adler/zlib/commit/9aaec95e82117c1cb0f9624264c3618fc380cecb
Signed-off-by: Mark Adler
Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
---
lib/zlib/inffast.c | 87 ++
1 file changed, 34 insertions(+), 53 deletions(-)
diff --git a/lib/zlib/inffa
://github.com/madler/zlib/commit/6a043145ca6e9c55184013841a67b2fef87e44c0
Signed-off-by: Mark Adler
Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
---
lib/zlib/inftrees.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/lib/zlib/inftrees.c b/lib/zlib
o 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70
Signed-off-by: Ley Foon Tan
---
v2:
- Mentioned new timing calculation is from databook in commit message.
---
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/soc
cl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.
Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)
After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70
Signed-o
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga-common-u-boot.dtsi | 4
arch/arm/mach-socfpga/Kconfig | 1
In Commit d64077202158 ("spi: cadence_qspi: Move to spi-mem framework")
it removes setting to quad write bit by accident. This commit restores
it back and also adding checking for octal support.
Fixes: d64077202158 ("spi: cadence_qspi: Move to spi-mem framework")
Signed-
commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override
bit")
Commit above removed writel to regs->pl310_aux_ctrl by accidentally,
restore it back.
Signed-off-by: Ley Foon Tan
---
drivers/cache/cache-l2x0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/
On Mon, Apr 20, 2020 at 4:46 PM Ley Foon Tan wrote:
>
> dram_init_banksize() is called in board_init_f() boot sequences
> in Uboot, remove it from SDRAM driver.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/ddr/altera/sdram_arria10.c | 3 ---
> 1 file changed, 3 del
Enable configs to support USB in Arria 10.
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
Signed-off-by: Ley Foon Tan
---
configs/socfpga_arria10_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/socfpga_arria10_defconfig
b/configs
Add call to get_ram_size() function to check memory range
for valid RAM.
Signed-off-by: Ley Foon Tan
---
v2:
- Change SZ_1G to full SDRAM size in get_ram_size() argument.
---
drivers/ddr/altera/sdram_arria10.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff
Tiny printf doesn't support %i, change to %u.
Reviewed-by: Tom Rini
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera/sdram_arria10.c
index 3fa34a1ae390
dram_init_banksize() is called in board_init_f() boot sequences
in Uboot, remove it from SDRAM driver.
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera/sdram_arria10
Move sdram_arria10.h to drivers/ddr/altera directory.
No functionality change.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +-
arch/arm/mach-socfpga/misc_arria10.c | 2 +-
drivers/ddr/altera/sdram_arria10.c
Convert Arria 10 SDRAM driver to device model.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Signed-off-by: Ley Foon Tan
---
v2:
- Change debug() to printf() if failed to probe SDRAM driver in SPL.
- Change to use MACRO(n) to calculate register
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS is added in
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET() macro already.
Remove extra SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS in mpu1 address
computation.
Signed-off-by: Ley Foon Tan
---
v2:
- Update commit description
---
drivers/ddr/altera/sdram_arria10.c
Change to use reset DM function and remove unused
socfpga_reset_deassert_noc_ddr_scheduler().
Signed-off-by: Ley Foon Tan
---
v2:
- Call to reset_assert_bulk() if failed in _probe().
---
.../include/mach/reset_manager_arria10.h | 1 -
arch/arm/mach-socfpga/reset_manager_arria10.c | 7
use MACRO(n) to calculate register address. [Patch 2]
- Call to reset_assert_bulk() if failed in _probe(). [Patch 3]
- Change SZ_1G to full SDRAM size in get_ram_size() argument. [Patch 5]
- Patch 4, 6 and 7 unchanged.
Ley Foon Tan (7):
ddr: altera: arria10: Fix incorrect address for mpu1
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.
Reported-by: Chee Hong Ang
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach
The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].
[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf
Signed-off-by: Ley Foon Tan
---
drivers/cache/cache-l2x0.c | 4
dram_init_banksize() is called in board_init_f() boot sequences
in Uboot, remove it from SDRAM driver.
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera/sdram_arria10
Tiny printf doesn't support %i, change to %u.
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera/sdram_arria10.c
index e3f11984a978..8acf324117af 100644
Add call to get_ram_size() function to check memory range
for valid RAM.
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera
Change to use reset DM function and remove unused
socfpga_reset_deassert_noc_ddr_scheduler().
Signed-off-by: Ley Foon Tan
---
.../include/mach/reset_manager_arria10.h | 1 -
arch/arm/mach-socfpga/reset_manager_arria10.c | 7 --
drivers/ddr/altera/sdram_arria10.c| 25
Move sdram_arria10.h to drivers/ddr/altera directory.
No functionality change.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +-
arch/arm/mach-socfpga/misc_arria10.c | 2 +-
drivers/ddr/altera/sdram_arria10.c
Convert Arria 10 SDRAM driver to device model.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 8 +
.../mach-socfpga/include/mach/sdram_arria10.h | 244
This patchset mainly to covert Arria 10 SDRAM driver to device model
and fixes few bugs in driver. It also added RAM size check function
to check valid RAM.
Ley Foon Tan (7):
ddr: altera: arria10: Fix incorrect address for mpu1
ddr: altera: arria10: Move SDRAM driver to DM
ddr: altera
Remove extra "SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS" in mpu1 address.
Signed-off-by: Ley Foon Tan
---
drivers/ddr/altera/sdram_arria10.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_arria10.c
b/drivers/ddr/altera/sdram_arria10.c
index 2fd50b7ae550..e0
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan
---
v2: Enable SPL_CACHE in Kconfig instead of defconfig.
---
arch/arm/dts/socfpga_arria10-u-boo
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
arch/arm/dts/socfpga_arria10.dtsi | 28
.../arm/dts
CONFIG_SPL_CACHE in Kconfig instead of defconfig.
History:
v1: https://patchwork.ozlabs.org/cover/1266732/
Thanks.
Regards
Ley Foon
Ley Foon Tan (3):
arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
arm: dts: arria10: Update dtsi/dts from Linux
arm: socfpga: arria10: Enable cache
.
Change in socfpga_arria10-u-boot.dtsi:
- Add compatible and altr,sysmgr-syscon for uboot.
Signed-off-by: Ley Foon Tan
---
v2: Update commit ID in description.
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15
arch/arm/dts/socfpga_arria10.dtsi| 90 ++--
arch/arm
,sysmgr-syscon for uboot.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15
arch/arm/dts/socfpga_arria10.dtsi| 90 ++--
arch/arm/dts/socfpga_arria10_socdk.dtsi | 43 +++---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 16
This patchset mainly to update Arria 10 dts/dtsi from Linux v5.6.
All uboot specific properties are moved to *u-boot.dtsi.
The 3rd patch is to fix missing u-boot,dm-pre-reloc for L2 cache node
and enable cache driver in SPL.
Thanks.
Regards
Ley Foon
Ley Foon Tan (3):
arm: dts: arria10: Move
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
arch/arm/dts/socfpga_arria10.dtsi | 28
.../arm/dts
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4
configs/socfpga_arria10_defconfig| 1
On Fri, Mar 20, 2020 at 3:52 PM Ley Foon Tan wrote:
> > >>>>>> configured. This
> > >>>>>> is because the FPGA drives configuration bits, around the interfaces
> > >>>>>> datawidth
> > >>>
Enable QSPI for Agilex SoC devkit.
Signed-off-by: Ley Foon Tan
---
v2:
- Fixed missing ";".
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u
Enable QSPI for Agilex SoC devkit.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index 1908be4b8b27
On Tue, Mar 17, 2020 at 4:01 AM Simon Goldschmidt
wrote:
>
> Am 16.03.2020 um 20:55 schrieb Dalon L Westergreen:
> >
> >
> > On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote:
> >> On 3/16/20 8:04 PM, Simon Goldschmidt wrote:
> >>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen:
>
>
On Wed, Mar 11, 2020 at 5:58 PM Marek Vasut wrote:
>
> On 3/11/20 10:54 AM, Ley Foon Tan wrote:
> > On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt
> > wrote:
> >>
> >> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote:
> >>>
> >
>
On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt
wrote:
>
> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote:
> >
> > >>
> > >
> > > I can reproduce the issue if without setting applycfg bit. Access to
> > > F2sdram interface will cause system hang.
> > >
> > > From the Cyclone 5 Soc
On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen
wrote:
>
> I am reading through this thread, and want to point out that it is not that
> the
> FPGA bridge need be actively used in the fpga, but
> rather that this port be configured in the FPGA configuration. This is an
> important
.
More information about reset status register value can be found in reset
manager register description.
When running in debugger without bootrom, r0 to r3 are random values.
So, skip save the value when r0 is not bootrom shared data address.
Signed-off-by: Ley Foon Tan
---
v2:
- Add macro
This patchset add support save reset status value from bootrom for Arria 10.
v2:
- Add macro for BOOTROM_SHARED_MEM_SIZE.
- Change to use SOCFPGA_PHYS_OCRAM_SIZE macro.
- Change to static for rst_mgr_status.
History:
v1: https://patchwork.ozlabs.org/patch/1245681/
Ley Foon Tan (3):
arm
Add OCRAM size macro for Gen5 and Arria 10.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++
arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
b
Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size.
Signed-off-by: Ley Foon Tan
---
include/configs/socfpga_common.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index ec4184369539
On Wed, Mar 4, 2020 at 8:32 PM Marek Vasut wrote:
>
> On 3/4/20 1:36 AM, Tan, Ley Foon wrote:
> >
> >
> >> -Original Message-
> >> From: Marek Vasut
> >> Sent: Tuesday, March 3, 2020 8:13 PM
> >> To: Ley Foon Tan
> >> C
On Tue, Mar 3, 2020 at 8:16 PM Marek Vasut wrote:
>
> On 3/3/20 10:21 AM, Ley Foon Tan wrote:
> > On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
> >>
> >> On 3/2/20 10:33 AM, Ley Foon Tan wrote:
> >>> On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan
On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>
> On 3/2/20 10:33 AM, Ley Foon Tan wrote:
> > On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan wrote:
> >>
> >> Add QSPI boot settings for Arria 10 SoCDK.
> >>
> >> Signed-off-by: Ley Foon Tan
> &
On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>
> On 3/2/20 8:20 AM, Tan, Ley Foon wrote:
> Hi,
>
> [...]
>
> >> On 2/26/20 8:01 PM, Ley Foon Tan wrote:
> >> [...]
> >>> +#define BOOTROM_SHARED_MEM_AD
On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan wrote:
>
> Add QSPI boot support to boot target devices list.
> Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS
> macro if needed.
>
> Add SOCFPGA_BOOT_SETTINGS for Cyclone 5.
>
> Signed-off-by: Ley Fo
On Fri, Feb 21, 2020 at 9:26 AM Ley Foon Tan wrote:
>
> Enable random ethaddr CONFIG_NET_RANDOM_ETHADDR for Cyclone 5.
>
> Ethernet failed to work if ethaddr is empty when Ethernet driver is probed.
> Setting ethaddr in Uboot command prompt can't solve this.
> Enable rando
On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan wrote:
>
> Add QSPI boot settings for Arria 10 SoCDK.
>
> Signed-off-by: Ley Foon Tan
> ---
> include/configs/socfpga_arria10_socdk.h | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/include/configs/s
.
More information about reset status register value can be found in reset
manager register description.
When running in debugger without Bootrom, r0 to r3 are random values.
So, skip save the value when r0 is not BootROM shared data address.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga
me 'ethernet@ff702000'
No ethernet found.
Signed-off-by: Ley Foon Tan
---
configs/socfpga_cyclone5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/socfpga_cyclone5_defconfig
b/configs/socfpga_cyclone5_defconfig
index b6220e4ae8..9021703e38 100644
--- a/configs/socfpga_cyclone5_def
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