Re: [PATCH] riscv: fix the wrong swap value register

eletion(-) > Thanks for catching this issue! Reviewed-by: Lukas Auer

[PATCH] Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"

. Signed-off-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 1 - board/emulation/qemu-riscv/qemu-riscv.c | 39 - 2 files changed, 40 deletions(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 7ce12018e7

Re: [PATCH 2/2] riscv: Avoid calling sbi_clear_ipi()

nged, 2 insertions(+), 1 deletion(-) > Reviewed-by: Lukas Auer

Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}

t; Signed-off-by: Bin Meng > --- > > arch/riscv/include/asm/sbi.h | 19 --- > 1 file changed, 12 insertions(+), 7 deletions(-) > Reviewed-by: Lukas Auer

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Tue, 2020-03-03 at 16:57 -0500, Sean Anderson wrote: > On 3/3/20 4:53 PM, Lukas Auer wrote: > > On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote: > > > On 3/2/20 6:17 PM, Lukas Auer wrote: > > > > Don't move this. It is intended to be run before the IPI is c

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote: > On 3/2/20 6:17 PM, Lukas Auer wrote: > > On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote: > > > > > The IPI code could have race conditions in several places. > > > * Several harts could race on

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote: > The IPI code could have race conditions in several places. > * Several harts could race on the value of gd->arch->clint/plic > * Non-boot harts could race with the main hart on the DM subsystem In > addition, if an IPI was pending when

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote: > On 3/2/20 4:08 AM, Rick Chen wrote: > > Hi Sean > > > > > The IPI code could have race conditions in several places. > > > * Several harts could race on the value of gd->arch->clint/plic > > > * Non-boot harts could race with the main

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

On Sun, 2020-01-26 at 20:09 -0500, Sean Anderson wrote: > On 1/26/20 5:17 PM, Lukas Auer wrote: > > Hi Sean, > > > > > > On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote: > > > The Sipeed Maix series is a collection of boards built around the

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

On Sun, 2020-01-26 at 17:24 -0500, Sean Anderson wrote: > On 1/26/20 5:09 PM, Lukas Auer wrote: > > + Bin, Anup, Atish > > > > > > On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote: > > > On the kendryte k210, writes to mcounteren result in an illega

Re: [PATCH] riscv: Try to get cpu frequency from device tree

On Sun, 2020-01-26 at 13:20 -0500, Sean Anderson wrote: > On 1/26/20 11:34 AM, Lukas Auer wrote: > > Hi Sean, > > Usually, ret is used as a variable name here. I think it would actually > > make the code a bit nicer to read here, because the clock rate is not > > read fr

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

On Sun, 2020-01-26 at 17:12 -0500, Sean Anderson wrote: > On 1/26/20 5:04 PM, Lukas Auer wrote: > > asm/u-boot.h is usually included with common.h. ulong is defined in > > linux/types.h (also included in common.h). It should be sufficient to > > include common.h

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

Hi Sean, On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote: > The Sipeed Maix series is a collection of boards built around the RISC-V > Kendryte K210 processor. This processor contains several peripherals to > accelerate neural network processing and other "ai" tasks. This includes a >

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

+ Bin, Anup, Atish On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote: > On the kendryte k210, writes to mcounteren result in an illegal instruction > exception. > > Signed-off-by: Sean Anderson > --- > Changes for v2: > Moved forward in the patch series > > arch/riscv/Kconfig | 3 +++

Re: [PATCH v2 06/11] riscv: Fix incorrect cpu frequency on RV64

| 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Lukas Auer

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

Hi Sean, On Wed, 2020-01-15 at 17:50 -0500, Sean Anderson wrote: > This header depended on bd_t and ulong, but did not include the appropriate > headers. > > Signed-off-by: Sean Anderson > --- > arch/riscv/include/asm/global_data.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git

Re: [PATCH] riscv: Try to get cpu frequency from device tree

dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq); > + > + /* First try getting the frequency from the assigned clock */ > + err = clk_get_by_index(dev, 0, ); Usually, ret is used as a variable name here. I think it would actually make the code a bit nicer t

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

On Tue, 2020-01-14 at 23:12 -0600, Troy Benjegerdes wrote: > > On Jan 13, 2020, at 4:31 PM, Lukas Auer wrote: > > > > +Troy > > > > On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote: > > > > > > +#include >

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

+Troy On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote: > > > > +#include > > > > + > > > > +u32 DENALI_PHY_DATA[1215] = { > > > > + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, > > > DENALI_PHY_02_DATA, > > > > + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, > > > DENALI_PHY_05_DATA, >

[PATCH v2 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow

Lukas Auer (4): spl: opensbi: specify main hart as preferred boot hart riscv: add functions for reading the IPI status riscv: add option to wait for ack from secondary harts in smp functions spl: opensbi: wait for ack from secondary harts before entering OpenSBI arch/riscv/cpu

[PATCH v2 3/4] riscv: add option to wait for ack from secondary harts in smp functions

before calling the function from the request. Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel --- Changes in v2: None arch/riscv/cpu/start.S | 2 ++ arch/riscv/include/asm/smp.h | 3 ++- arch/riscv/lib/bootm.c | 2 +- arch/riscv

[PATCH v2 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI

always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: Rick Chen Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel --- Changes in v2: None common/spl

[PATCH v2 2/4] riscv: add functions for reading the IPI status

Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer --- Changes in v2: - Use

[PATCH v2 1/4] spl: opensbi: specify main hart as preferred boot hart

project to update the info structure. The header file is recent as of commit 7a13beb21326 ("firmware: Add preferred boot HART field in struct fw_dynamic_info"). Reported-by: Rick Chen Suggested-by: Anup Patel Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewe

[PATCH 1/4] spl: opensbi: specify main hart as preferred boot hart

project to update the info structure. The header file is recent as of commit 7a13beb21326 ("firmware: Add preferred boot HART field in struct fw_dynamic_info"). Reported-by: Rick Chen Suggested-by: Anup Patel Signed-off-by: Lukas Auer --- common/spl/spl_opensbi.c | 1 + include

[PATCH 2/4] riscv: add functions for reading the IPI status

Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer --- I do not have access

[PATCH 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow

of overlapping link address ranges. However, it is still recommended to select non-overlapping ranges for U-Boot SPL and OpenSBI. [1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html Lukas Auer (4): spl: opensbi: specify main hart as preferred boot hart riscv: add functions

[PATCH 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI

always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: Rick Chen Signed-off-by: Lukas Auer --- common/spl/spl_opensbi.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git

[PATCH 3/4] riscv: add option to wait for ack from secondary harts in smp functions

before calling the function from the request. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 2 ++ arch/riscv/include/asm/smp.h | 3 ++- arch/riscv/lib/bootm.c | 2 +- arch/riscv/lib/smp.c | 31 ++- arch/riscv/lib/spl.c | 2

[U-Boot] [PATCH] riscv: increase stack size to avoid a stack overflow during distro boot

by the secondary hart overwriting the return address in the stack frame of the main hart with an address that does not include valid code. Increase the default stack size of each hart to 16KiB to avoid this problem. Reported-by: Aurelien Jarno Signed-off-by: Lukas Auer Tested-by: David

[U-Boot] [RESEND PATCH v4 06/11] riscv: add SPL support

proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: None Changes in v3: None Changes in v2: None arch/Kconfig

[U-Boot] [RESEND PATCH v4 11/11] doc: update QEMU RISC-V documentation

The available defconfigs for RISC-V QEMU have changed. We now have configurations to compile U-Boot to run in supervisor mode and for U-Boot SPL. Update the QEMU RISC-V documentation to reflect these changes. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup

[U-Boot] [RESEND PATCH v4 09/11] riscv: set default FIT generator script and build target for SPL builds

Now that we have a generic FIT generator script for RISC-V, set it as the default. To also build the FIT image by default, set the default build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by:

[U-Boot] [RESEND PATCH v4 08/11] riscv: add a generic FIT generator script

_LOAD_ADDR and OPENSBI_LOAD_ADDR environment variables. The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh) and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator scripts. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --

[U-Boot] [RESEND PATCH v4 05/11] spl: support booting via RISC-V OpenSBI

/opensbi.h is based on header files from the OpenSBI project. They are recent, as of commit bae54f764570 ("firmware: Add fw_dynamic firmware"). Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: None Changes in v3: - Upd

[U-Boot] [RESEND PATCH v4 07/11] riscv: support SPL stack and global data relocation

that we cannot update the global data pointer of the main hart in spl_relocate_stack_gd(), because the secondary harts have not yet been relocated at this point. It is updated after the secondary harts have been notified. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed

[U-Boot] [RESEND PATCH v4 10/11] riscv: qemu: add SPL configuration

at address 0x8020. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested

[U-Boot] [RESEND PATCH v4 04/11] riscv: add run mode configuration for SPL

equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: None Changes in v3: - Rebase on u-boot-riscv

[U-Boot] [RESEND PATCH v4 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

to be aligned to ARCH_DMA_MINALIGN. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: None Changes in v3: None Changes in v2: None common/spl/spl_fit.c | 37 - 1 file changed, 24 insertions(+), 13

[U-Boot] [RESEND PATCH v4 02/11] Makefile: support building SPL FIT images without device trees

tree provider. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: - Also build the device tree if CONFIG_OF_HOSTFILE is selected, otherwise sandbox_spl is broken Changes in v3: None Changes in v2: None Makefile | 8 ++-- 1 file

[U-Boot] [RESEND PATCH v4 00/11] SPL support for RISC-V

of OpenSBI - Rebase on u-boot/master - Add note on minimum version of OpenSBI Changes in v2: - Rebase on master and format documentation as reStructuredText Lukas Auer (11): fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL Makefile: support building SPL FIT images without device trees spl: fit

[U-Boot] [RESEND PATCH v4 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being used in U-Boot SPL. Change the logic to also make it available in U-Boot SPL. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: None Changes in v3: None

[U-Boot] [PATCH v4 02/11] Makefile: support building SPL FIT images without device trees

tree provider. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v4: - Also build the device tree if CONFIG_OF_HOSTFILE is selected, otherwise this breaks sandbox_spl Changes in v3: None Changes in v2: None Makefile | 8 ++-- 1

[U-Boot] [PATCH v3 05/11] spl: support booting via RISC-V OpenSBI

/opensbi.h is based on header files from the OpenSBI project. They are recent, as of commit bae54f764570 ("firmware: Add fw_dynamic firmware"). Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: - Update commit message

[U-Boot] [PATCH v3 00/11] SPL support for RISC-V

and format documentation as reStructuredText Lukas Auer (11): fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL Makefile: support building SPL FIT images without device trees spl: fit: use U-Boot device tree when FIT image has no device tree riscv: add run mode configuration for SPL spl

[U-Boot] [PATCH v3 04/11] riscv: add run mode configuration for SPL

equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: - Rebase on u-boot-riscv/master Changes in v2

[U-Boot] [PATCH v3 06/11] riscv: add SPL support

proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: None Changes in v2: None arch/Kconfig | 6 +++ arch/riscv

[U-Boot] [PATCH v3 09/11] riscv: set default FIT generator script and build target for SPL builds

Now that we have a generic FIT generator script for RISC-V, set it as the default. To also build the FIT image by default, set the default build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by:

[U-Boot] [PATCH v3 08/11] riscv: add a generic FIT generator script

_LOAD_ADDR and OPENSBI_LOAD_ADDR environment variables. The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh) and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator scripts. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --

[U-Boot] [PATCH v3 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

to be aligned to ARCH_DMA_MINALIGN. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: None Changes in v2: None common/spl/spl_fit.c | 37 - 1 file changed, 24 insertions(+), 13 deletions(-) diff --git

[U-Boot] [PATCH v3 02/11] Makefile: support building SPL FIT images without device trees

. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: None Changes in v2: None Makefile | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 8513db94e3..b2f857f890 100644 --- a/Makefile

[U-Boot] [PATCH v3 11/11] doc: update QEMU RISC-V documentation

The available defconfigs for RISC-V QEMU have changed. We now have configurations to compile U-Boot to run in supervisor mode and for U-Boot SPL. Update the QEMU RISC-V documentation to reflect these changes. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup

[U-Boot] [PATCH v3 10/11] riscv: qemu: add SPL configuration

at address 0x8020. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested

[U-Boot] [PATCH v3 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being used in U-Boot SPL. Change the logic to also make it available in U-Boot SPL. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v3: None Changes in v2: None

[U-Boot] [PATCH v3 07/11] riscv: support SPL stack and global data relocation

that we cannot update the global data pointer of the main hart in spl_relocate_stack_gd(), because the secondary harts have not yet been relocated at this point. It is updated after the secondary harts have been notified. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed

[U-Boot] [PATCH v2 05/11] spl: support booting via RISC-V OpenSBI

the OpenSBI project. They are recent, as of commit bae54f764570 ("firmware: Add fw_dynamic firmware"). Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None common/image.c | 1 + common/spl/Kconfig | 17 common/spl/Makefile

[U-Boot] [PATCH v2 00/11] SPL support for RISC-V

-kernel spl/u-boot-spl \ -device loader,file=u-boot.itb,addr=0x8020 Changes in v2: - Rebase on master and format documentation as reStructuredText Lukas Auer (11): fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL Makefile: support building SPL FIT images without device trees

[U-Boot] [PATCH v2 08/11] riscv: add a generic FIT generator script

_LOAD_ADDR and OPENSBI_LOAD_ADDR environment variables. The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh) and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator scripts. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: N

[U-Boot] [PATCH v2 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

to be aligned to ARCH_DMA_MINALIGN. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None common/spl/spl_fit.c | 37 - 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c

[U-Boot] [PATCH v2 11/11] doc: update QEMU RISC-V documentation

The available defconfigs for RISC-V QEMU have changed. We now have configurations to compile U-Boot to run in supervisor mode and for U-Boot SPL. Update the QEMU RISC-V documentation to reflect these changes. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes

[U-Boot] [PATCH v2 10/11] riscv: qemu: add SPL configuration

at address 0x8020. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested

[U-Boot] [PATCH v2 04/11] riscv: add run mode configuration for SPL

equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None arch/riscv/Kconfig| 33

[U-Boot] [PATCH v2 07/11] riscv: support SPL stack and global data relocation

that we cannot update the global data pointer of the main hart in spl_relocate_stack_gd(), because the secondary harts have not yet been relocated at this point. It is updated after the secondary harts have been notified. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes

[U-Boot] [PATCH v2 09/11] riscv: set default FIT generator script and build target for SPL builds

Now that we have a generic FIT generator script for RISC-V, set it as the default. To also build the FIT image by default, set the default build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Cha

[U-Boot] [PATCH v2 06/11] riscv: add SPL support

proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None arch/Kconfig | 6 +++ arch/riscv/Kconfig | 3 ++ arch/riscv/cpu

[U-Boot] [PATCH v2 02/11] Makefile: support building SPL FIT images without device trees

. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None Makefile | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 704579bec1..84678b2c47 100644 --- a/Makefile +++ b/Makefile @@ -1263,7 +1263,9

[U-Boot] [PATCH v2 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being used in U-Boot SPL. Change the logic to also make it available in U-Boot SPL. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None include/fdtdec.h | 2 +- lib/fdtdec.c | 6

[U-Boot] [RFC PATCH 05/11] spl: support booting via RISC-V OpenSBI

the OpenSBI project. They are recent, as of commit bae54f764570 ("firmware: Add fw_dynamic firmware"). Signed-off-by: Lukas Auer --- common/image.c | 1 + common/spl/Kconfig | 17 common/spl/Makefile | 1 + common/spl/spl.c | 6 +++ common/spl/spl_open

[U-Boot] [RFC PATCH 00/11] SPL support for RISC-V

with the following command. qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \ -device loader,file=u-boot.itb,addr=0x8020 Lukas Auer (11): fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL Makefile: support building SPL FIT images without device trees spl

[U-Boot] [RFC PATCH 11/11] doc: update QEMU RISC-V documentation

The available defconfigs for RISC-V QEMU have changed. We now have configurations to compile U-Boot to run in supervisor mode and for U-Boot SPL. Update the QEMU RISC-V documentation to reflect these changes. Signed-off-by: Lukas Auer --- doc/README.qemu-riscv | 56

[U-Boot] [RFC PATCH 09/11] riscv: set default FIT generator script and build target for SPL builds

Now that we have a generic FIT generator script for RISC-V, set it as the default. To also build the FIT image by default, set the default build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled. Signed-off-by: Lukas Auer --- Kconfig | 4 +++- 1 file changed, 3 insertions(+),

[U-Boot] [RFC PATCH 10/11] riscv: qemu: add SPL configuration

at address 0x8020. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer --- board/emulation/qemu

[U-Boot] [RFC PATCH 08/11] riscv: add a generic FIT generator script

_LOAD_ADDR and OPENSBI_LOAD_ADDR environment variables. The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh) and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator scripts. Signed-off-by: Lukas Auer --- arch/riscv/lib/mkimage_fit_opensb

[U-Boot] [RFC PATCH 07/11] riscv: support SPL stack and global data relocation

that we cannot update the global data pointer of the main hart in spl_relocate_stack_gd(), because the secondary harts have not yet been relocated at this point. It is updated after the secondary harts have been notified. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 35

[U-Boot] [RFC PATCH 06/11] riscv: add SPL support

proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer --- arch/Kconfig | 6 +++ arch/riscv/Kconfig | 3 ++ arch/riscv/cpu/generic/Kconfig | 3 ++ arch/riscv/cpu/start.S | 23

[U-Boot] [RFC PATCH 04/11] riscv: add run mode configuration for SPL

equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig| 33 ++- arch/riscv/cpu/ax25/Kconfig | 6 +++--- arch/riscv/cpu

[U-Boot] [RFC PATCH 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

to be aligned to ARCH_DMA_MINALIGN. Signed-off-by: Lukas Auer --- common/spl/spl_fit.c | 37 - 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 969f7775c1..0bfb91d686 100644 --- a/common/spl/spl_fit.c

[U-Boot] [RFC PATCH 02/11] Makefile: support building SPL FIT images without device trees

. Signed-off-by: Lukas Auer --- Makefile | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 73fdf70cdd..23f4a73b7a 100644 --- a/Makefile +++ b/Makefile @@ -1263,7 +1263,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW

[U-Boot] [RFC PATCH 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being used in U-Boot SPL. Change the logic to also make it available in U-Boot SPL. Signed-off-by: Lukas Auer --- include/fdtdec.h | 2 +- lib/fdtdec.c | 6 ++ 2 files changed, 3 insertions(+), 5 deletions(-) diff

[U-Boot] [PATCH] simple-bus: add DM_FLAG_PRE_RELOC flag to simple-bus driver

. Add the DM_FLAG_PRE_RELOC flag to the simple-bus driver to make devices under it with drivers that have set the flag as well available pre relocation for these boards. Signed-off-by: Lukas Auer --- drivers/core/simple-bus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/core/simple

[U-Boot] [PATCH v3 09/11] riscv: hang if relocation of secondary harts fails

Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: Lukas Auer --- Changes in v3: - New patch to hang if relocation of secondary harts fails Changes in v2: None arch/riscv/cpu/start.S | 13

[U-Boot] [PATCH v3 07/11] riscv: boot images passed to bootm on all harts

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v3: None Changes in v2: None arch/riscv/lib/bootm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c

[U-Boot] [PATCH v3 08/11] riscv: do not rely on hart ID passed by previous boot stage

. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin

[U-Boot] [PATCH v3 10/11] riscv: fu540: enable SMP

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: - New patch to enable SMP on the SiFive FU540, which was previously sent independently board/sifive/fu540/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sifive

[U-Boot] [PATCH v3 11/11] riscv: qemu: enable SMP

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v3: None Changes in v2: None board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv

[U-Boot] [PATCH v3 03/11] riscv: implement IPI platform functions using SBI

mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Atish Patra Tested-by: Bin Meng --- Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 5 + arch/riscv/lib/Makefile

[U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0

instead to protect the hart ID. Signed-off-by: Lukas Auer --- Changes in v3: - New patch to save the hart ID in register tp instead of s0 Changes in v2: None arch/riscv/cpu/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu

[U-Boot] [PATCH v3 06/11] riscv: add support for multi-hart systems

in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas

[U-Boot] [PATCH v3 02/11] riscv: import the supervisor binary interface header file

Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: A

[U-Boot] [PATCH v3 04/11] riscv: delay initialization of caches and debug UART

. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: None arch/riscv/cpu/start.S | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 81ea52b170

[U-Boot] [PATCH v3 00/11] SMP support for RISC-V

to populate register a0 with the hart ID from the mhartid CSR in machine-mode - New patch to enable SMP on the SiFive FU540, which was previously sent independently Lukas Auer (11): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface

[U-Boot] [PATCH v3 01/11] riscv: add infrastructure for calling functions on other harts

(all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v3: - Print error if riscv_send_ipi() fails

[U-Boot] [PATCH v2 6/9] riscv: boot images passed to bootm on all harts

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v2: None arch/riscv/lib/bootm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index f36b8702ef..efbd3e23e7 100644

[U-Boot] [PATCH v2 8/9] riscv: fu540: enable SMP

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v2: - New patch to enable SMP on the SiFive FU540, which was previously sent independently board/sifive/fu540/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig

[U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage

. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen Signed-off-by: Lukas Auer --- Changes in v2: - New patch to populate register a0 with the hart ID from the mhartid

[U-Boot] [PATCH v2 3/9] riscv: implement IPI platform functions using SBI

mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v2: None arch/riscv/Kconfig | 5 + arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sbi_ipi.c | 25 + 3

[U-Boot] [PATCH v2 9/9] riscv: qemu: enable SMP

Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v2: None board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 88d07d568e..cf057e7de6 100644

[U-Boot] [PATCH v2 5/9] riscv: add support for multi-hart systems

in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas

[U-Boot] [PATCH v2 2/9] riscv: import the supervisor binary interface header file

Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes i

[U-Boot] [PATCH v2 4/9] riscv: delay initialization of caches and debug UART

. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- Changes in v2: None arch/riscv/cpu/start.S | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 81ea52b170..a30f6f7194 100644 --- a/arch

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