On Mon, Jul 29, 2013 at 10:09 AM, Albert ARIBAUD
wrote:
> Hi Michael,
>
> On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang
> wrote:
>
>> Albert,
>>
>> That's not a correct characterization of the bug.
>>
>> The incoherent cache lines are
at 3:19 AM, Albert ARIBAUD
wrote:
> (although this patch is more than two *years* old, it never got properly
> answered to. I am doing so here to make sure future readers know why it
> was not applied and won't be.)
>
> Hi Michael,
>
> On Thu, 17 Mar 2011 15:46:55 -0400, Micha
On Sun, Apr 24, 2011 at 7:55 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-7-git-send-email-msp...@csclub.uwaterloo.ca> you
> wrote:
>> The TS-7800 needs to skip SDRAM initialization since it loads from
>> RAM, but the CPU shou
On Mon, Apr 25, 2011 at 7:37 AM, Tabi Timur-B04825 wrote:
> On Sun, Apr 24, 2011 at 6:50 PM, Wolfgang Denk wrote:
>
>> And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to
>> the README.
>
> We have something similar already on Freescale parts, but it does
> sometimes cause probl
On Sun, Apr 24, 2011 at 7:50 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-3-git-send-email-msp...@csclub.uwaterloo.ca> you
> wrote:
>> The MVGBE driver either gets the MAC from the environment, or invents
>> one. This allows th
On Sun, Apr 24, 2011 at 8:01 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-10-git-send-email-msp...@csclub.uwaterloo.ca>
> you wrote:
>> Signed-off-by: Michael Spang
>> --
On Sun, Apr 24, 2011 at 7:59 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-9-git-send-email-msp...@csclub.uwaterloo.ca> you
> wrote:
>> The NAND control functions were written by Alexander Clouter and
>> copied here from Linux.
>
On Sun, Apr 24, 2011 at 7:53 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-6-git-send-email-msp...@csclub.uwaterloo.ca> you
> wrote:
>> For ARM, the CONFIG_SKIP_LOWLEVEL_INIT option implies that the
>> cpu_init_crit and lowlev
On Sun, Apr 24, 2011 at 7:57 PM, Wolfgang Denk wrote:
> Dear Michael Spang,
>
> In message <1300391223-11879-8-git-send-email-msp...@csclub.uwaterloo.ca> you
> wrote:
>> The TS-7800 is an Orion5x implementation by Technologic Systems.
>>
>> Signed-off-b
On 3/20/11, arden jay wrote:
> Hi Michael,
>
> I still have question. :)
>
> When ARM fetch instruction, it firstly try cache.
> It then should have cache miss, and forces to reload the instruction
> from memory?
>
> Why it will have problem while U-boot & Kernel at the same memory location?
If t
On 3/19/11, arden jay wrote:
> Hi Michael,
> Curiously, have any idea how to test cache stuff?
I don't have any good suggestions for testing cache stuff in general,
but this one is pretty easy to test if you have the board in question.
Because U-Boot is loaded *as if it were linux* by the manufac
On Fri, Mar 18, 2011 at 1:57 AM, Rogan Dawes wrote:
> On 2011/01/29 9:24 AM, Albert ARIBAUD wrote:
>> Hi Michael,
>>
>> Le 29/01/2011 02:00, Michael Spang a écrit :
>>> This code intends to read the SDRAM controller base address registers
>>> but is inst
On Sat, Jan 29, 2011 at 2:36 AM, Albert ARIBAUD wrote:
> Le 29/01/2011 02:00, Michael Spang a écrit :
>>
>> For the TS-7800, the FPGA contains a bootloader which handles
>> the SDRAM initialization and loads a bootloader from RAM. We
>> should not try to initialize RAM
: Michael Spang
---
Makefile|2 +-
README |8 +++-
arch/arm/cpu/arm1136/start.S|6 +++---
arch/arm/cpu/arm720t/start.S|2 +-
arch/arm/cpu/arm920t/at91
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by: Michael Spang
---
MAKEALL |1 +
board/technologic/ts7800/Makefile | 46 +++
board/technologic/ts7800/ts7800.c | 36 +
boards.cfg|1
MAC is set.
Michael Spang (9):
arm926ej-s: Invalidate instruction cache in flush_cache
mvgbe: Support preserving the existing MAC address
orion5x: Increase maximum bank size to 128M
orion5x: Fix wrong address in orion5x_sdram_bar
ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_
The TS-7800 has one 128M RAM bank, so the maximum must be increased.
Signed-off-by: Michael Spang
---
arch/arm/include/asm/arch-orion5x/orion5x.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h
b/arch/arm/include/asm/arch
The NAND control functions were written by Alexander Clouter and
copied here from Linux.
Signed-off-by: Michael Spang
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/ts7800_nand.c | 68
include/configs/ts7800.h | 47
If U-Boot is loaded from RAM and the OS is loaded into an overlapping
region, the instruction cache is not coherent when that OS is started.
We must therefore invalidate the instruction cache in addition to
cleaning the data cache.
Signed-off-by: Michael Spang
---
arch/arm/lib/cache.c |2
Signed-off-by: Michael Spang
---
doc/README.ts7800 | 84 +
1 files changed, 84 insertions(+), 0 deletions(-)
create mode 100644 doc/README.ts7800
diff --git a/doc/README.ts7800 b/doc/README.ts7800
new file mode 100644
index 000..6a6ab94
The TS-7800 needs to skip SDRAM initialization since it loads from
RAM, but the CPU should still be initialized to the correct state.
Thus we add an #ifdef around the call to the lowlevel_init function.
Signed-off-by: Michael Spang
---
arch/arm/cpu/arm926ejs/at91/Makefile|2 ++
arch/arm
This code intends to read the SDRAM controller base address registers
but is instead reading the CPU window base address registers. Also,
remove "ddr" from the name of struct orion5x_addr_decode_registers,
since it also applies to other decode registers.
Signed-off-by: Michael Spang
The MVGBE driver either gets the MAC from the environment, or invents
one. This allows the driver to leave the existing address alone in
case it is initialized before U-Boot starts.
Signed-off-by: Michael Spang
---
drivers/net/mvgbe.c | 20
1 files changed, 20 insertions
On Thu, Mar 17, 2011 at 3:46 PM, Michael Spang
wrote:
> The TS-7800 is an Orion5x implementation by Technologic Systems.
>
> Albert, Wolfgang -
>
> Thanks for reviewing my patch series and sorry for the delay
> in updating it.
>
> Changelog:
> - Fixed all chec
On Sat, Jan 29, 2011 at 2:39 AM, Albert ARIBAUD wrote:
> Le 29/01/2011 02:00, Michael Spang a écrit :
>>
>> The TS-7800 is an Orion5x implementation by Technologic Systems.
>>
>> Signed-off-by: Michael Spang
>> ---
>> MAKEALL
On Sat, Jan 29, 2011 at 2:24 AM, Albert ARIBAUD wrote:
>> diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c
>> b/arch/arm/cpu/arm926ejs/orion5x/dram.c
>> index b749282..7f3a318 100644
>> --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
>> +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
>> @@ -38,7 +38,7 @
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by: Michael Spang
---
MAKEALL |1 +
board/technologic/ts7800/Makefile | 46 +++
board/technologic/ts7800/ts7800.c | 36 +
boards.cfg|1
The NAND control functions were written by Alexander Clouter and
copied here from Linux.
Signed-off-by: Michael Spang
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/ts7800_nand.c | 68
include/configs/ts7800.h | 46
If U-Boot is loaded from RAM and the OS is loaded into an overlapping
region, the instruction cache is not coherent when that OS is started.
We must therefore invalidate the instruction cache in addition to
cleaning the data cache.
Signed-off-by: Michael Spang
---
arch/arm/lib/cache.c |2
The MVGBE driver either gets the MAC from the environment, or invents
one. This allows the driver to leave the existing address alone in
case it is initialized before U-Boot starts.
Signed-off-by: Michael Spang
---
drivers/net/mvgbe.c | 20
1 files changed, 20 insertions
This code intends to read the SDRAM controller base address registers
but is instead reading the CPU window base address registers.
Signed-off-by: Michael Spang
---
arch/arm/cpu/arm926ejs/orion5x/dram.c |2 +-
arch/arm/include/asm/arch-orion5x/orion5x.h |1 +
2 files changed, 2
Signed-off-by: Michael Spang
---
doc/README.ts7800 | 60 +
1 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 doc/README.ts7800
diff --git a/doc/README.ts7800 b/doc/README.ts7800
new file mode 100644
index 000..25b9883
For the TS-7800, the FPGA contains a bootloader which handles
the SDRAM initialization and loads a bootloader from RAM. We
should not try to initialize RAM again while running from it.
Signed-off-by: Michael Spang
---
arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S |4
1 files changed
The TS-7800 has one 128M RAM bank, so the maximum must be increased.
Signed-off-by: Michael Spang
---
arch/arm/include/asm/arch-orion5x/orion5x.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h
b/arch/arm/include/asm/arch
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