Hi Jernej,
在 2017年03月09日 07:34, Jernej Skrabec 写道:
Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.
DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.
EDID reading code
Hi Simon,
在 2017年02月24日 00:19, Simon Glass 写道:
Hi Nickey,
On 22 February 2017 at 23:56, Nickey.Yang wrote:
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass wrote:
On 28 December 2016 at 23:01, Nickey Yang
wrote:
Correct mpixelclock errors
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass wrote:
On 28 December 2016 at 23:01, Nickey Yang wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang
---
drivers/video/rockchip/rk_hdmi
Hi Kever & Simon,
在 2016年12月14日 15:07, Kever Yang 写道:
Hi Simon,
On 12/12/2016 04:27 AM, Simon Glass wrote:
Hi Nickey,
On 8 December 2016 at 21:39, Nickey Yang
wrote:
isp-camera image will be broken when enter dual screen display mode.
We set isp qos high to solve this problem.
Signed-off
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