On Tue, 07 Nov 2023 15:12:16 PST (-0800), Conor Dooley wrote:
+CC Palmer
On Tue, Nov 07, 2023 at 05:38:37PM -0500, Tom Rini wrote:
On Tue, Nov 07, 2023 at 10:27:50PM +, Conor Dooley wrote:
> On Tue, Nov 07, 2023 at 05:10:23PM -0500, Tom Rini wrote:
>
>
> > further clarify or not
> > the
ions - for example the
> Zicsr and Zifencei extensions were spun out of the base ISA.
>
> [...]
Applied, thanks!
[1/1] dt-bindings: riscv: deprecate riscv,isa
https://git.kernel.org/palmer/c/aeb71e42caae
Best regards,
--
Palmer Dabbelt
e the aspect of riscv,isa that is
not represented by the new property - the base ISA implemented by a hart.
As a starting point, add properties for extensions currently used in
Linux.
Finally, mark riscv,isa as deprecated, as removing support for it in
existing programs would be an ABI break.
On Wed, 28 Jun 2023 08:31:32 PDT (-0700), apa...@ventanamicro.com wrote:
On Wed, Jun 28, 2023 at 7:46 PM Palmer Dabbelt wrote:
On Tue, 27 Jun 2023 08:49:06 PDT (-0700), Palmer Dabbelt wrote:
> On Mon, 26 Jun 2023 23:52:06 PDT (-0700), apa...@ventanamicro.com wrote:
>> On Tue, Jun
On Tue, 27 Jun 2023 08:49:06 PDT (-0700), Palmer Dabbelt wrote:
> On Mon, 26 Jun 2023 23:52:06 PDT (-0700), apa...@ventanamicro.com wrote:
>> On Tue, Jun 27, 2023 at 1:23â¯AM Palmer Dabbelt wrote:
>>>
>>> On Mon, 26 Jun 2023 10:38:43 PDT (-0700), apa...@ventanamicro.c
a hart.
As a starting point, add properties for extensions currently used in
Linux.
Finally, mark riscv,isa as deprecated, as removing support for it in
existing programs would be an ABI break.
CC: Palmer Dabbelt
CC: Paul Walmsley
CC: Rob Herring
CC: Krzysztof Kozlowski
CC: Alistair Francis
CC:
On Thu, 22 Jun 2023 11:59:32 PDT (-0700), Conor Dooley wrote:
On Thu, Jun 22, 2023 at 11:25:35AM -0700, Palmer Dabbelt wrote:
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
I'm not wed to any particular encoding for the properties, IMO that's more
of a decision for the DT folks. IMO
isa-extension-" prefix saves the guts of
20 bytes per extension, per hart, and hopefully placates the size
conscious.
As a starting point, add properties for extensions currently used in
Linux.
Finally, mark riscv,isa as deprecated, as removing it is an ABI break.
CC: Palmer Dabbelt
CC: Paul Walmsl
On Thu, 18 May 2023 07:06:17 PDT (-0700), Conor Dooley wrote:
On Thu, May 18, 2023 at 07:13:15PM +0530, Anup Patel wrote:
On Thu, May 18, 2023 at 4:02 PM Andrew Jones wrote:
> On Thu, May 18, 2023 at 09:58:30AM +0100, Conor Dooley wrote:
> > - riscv,isa:
> > -description:
> > -
ed code.
>
> Cc: Alexey Brodkin
> Cc: Anup Patel
> Cc: Atish Patra
> Cc: Bin Meng
> Cc: Daniel Schwierzeck
> Cc: Leo
> Cc: Palmer Dabbelt
> Cc: Paul Walmsley
> Cc: Rick Chen
> Cc: Sean Anderson
> Cc: Simon Glass
> Signed-off-by: Tom Rini
> ---
be the most
important thing to focus on now, though.
Mark
On Thu, Sep 30, 2021 at 10:30 AM Palmer Dabbelt wrote:
On Thu, 30 Sep 2021 08:06:42 PDT (-0700), markhimelst...@riscv.org wrote:
> Palmer,
>
>
>
> Thank you for your input.
>
>
>
> Our strong intentio
-V. We also, as
I have described to you many times, have instituted mandatory standards
specification states for the front page of each specification to ensure
clarity (any divergence from this is a bug and we work to fix these
quickly).
On Tue, Sep 28, 2021 at 11:34 AM Palmer Dabbelt wrote:
On Tue, 28 Sep 2021 16:23:56 PDT (-0700), ati...@atishpatra.org wrote:
On Tue, Sep 28, 2021 at 3:43 PM Palmer Dabbelt wrote:
On Tue, 28 Sep 2021 13:05:53 PDT (-0700), ati...@atishpatra.org wrote:
> On Tue, Sep 28, 2021 at 11:34 AM Palmer Dabbelt wrote:
>>
>> On Mon, 27 Sep 20
On Tue, 28 Sep 2021 13:05:53 PDT (-0700), ati...@atishpatra.org wrote:
On Tue, Sep 28, 2021 at 11:34 AM Palmer Dabbelt wrote:
On Mon, 27 Sep 2021 08:57:15 PDT (-0700), markhimelst...@riscv.org wrote:
> the words in this document :
>
>
https://wiki.riscv.org/plugins/servlet/mobile?
, as then I
can at least focus the discussion on what's relevant right now.)
Mark
sent from a mobile device. please forgive any typos.
On Sep 27, 2021, at 8:50 AM, Palmer Dabbelt wrote:
On Tue, 21 Sep 2021 17:20:17 PDT (-0700), ati...@atishpatra.org wrote:
Hi All,
Please find the below
On Tue, 21 Sep 2021 17:20:17 PDT (-0700), ati...@atishpatra.org wrote:
Hi All,
Please find the below email from Stephano about the freeze announcement for
various RISC-V specifications that will be part of privilege specification
v1.12.
All the review discussions are happening in the isa-dev
Looks like our first attempt at sending a message bounced, so this never
got properly announced. We've got Microconference at Plumbers again
this year, the CFP is still open.
On Thu, 22 Apr 2021 20:40:43 PDT (-0700), Palmer Dabbelt wrote:
On Thu, 22 Apr 2021 02:11:51 PDT (-0700), green@sifive.com wrote:
This patch set is to add SiFive fu740 chip and HiFive Unmatched board
support. Patches are split into several parts:
- [PATCH v7 1/8] support for fu740 cpu
On Thu, 22 Apr 2021 02:11:51 PDT (-0700), green@sifive.com wrote:
This patch set is to add SiFive fu740 chip and HiFive Unmatched board
support. Patches are split into several parts:
- [PATCH v7 1/8] support for fu740 cpu
- [PATCH v7 2/8] support for fu740 clk driver
- [PATCH v7 3/8]
/board/sifive/fu540/MAINTAINERS
index 702d803ad8..5381fc0639 100644
--- a/board/sifive/fu540/MAINTAINERS
+++ b/board/sifive/fu540/MAINTAINERS
@@ -1,6 +1,6 @@
SiFive FU540 BOARD
M: Paul Walmsley
-M: Palmer Dabbelt
+M: Palmer Dabbelt
M: Anup Patel
M: Atish Patra
S
/MAINTAINERS
index 702d803ad8..9bae3d3db7 100644
--- a/board/sifive/fu540/MAINTAINERS
+++ b/board/sifive/fu540/MAINTAINERS
@@ -1,6 +1,6 @@
SiFive FU540 BOARD
M: Paul Walmsley
-M: Palmer Dabbelt
+M: Palmer Dabbelt
M: Anup Patel
M: Atish Patra
S: Maintained
Thanks
On Mon, 03 Jun 2019 10:02:57 PDT (-0700), tr...@konsulko.com wrote:
On Mon, Jun 03, 2019 at 09:44:28AM -0500, Troy Benjegerdes wrote:
> On Jun 3, 2019, at 5:49 AM, Andreas Schwab wrote:
>
> On Mai 29 2019, Karsten Merker wrote:
>
>> Mainline U-Boot already uses the distro bootcmd
On Sun, 17 Mar 2019 11:28:31 PDT (-0700), lukas.a...@aisec.fraunhofer.de wrote:
This patch series adds SMP support for RISC-V to U-Boot. It allows
U-Boot to run on multi-hart systems (hart is the RISC-V terminology for
hardware thread). Images passed to bootm will be started on all harts.
The
On Mon, 11 Mar 2019 07:33:25 PDT (-0700), bmeng...@gmail.com wrote:
On Thu, Feb 14, 2019 at 7:58 AM Kevin Hilman wrote:
Kevin Hilman writes:
> Hi Anup,
>
> Anup Patel writes:
>
>> This patchset adds SiFive Freedom Unleashed (FU540) support
>> to RISC-V U-Boot.
>>
>> The patches are based
On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote:
-Original Message-
From: Andreas Schwab
Sent: Thursday, March 7, 2019 2:50 PM
To: Anup Patel
Cc: Atish Patra ; Anup Patel ;
Auer, Lukas ; paul.walms...@sifive.com;
ag...@suse.de; u-boot@lists.denx.de; bar...@tkos.co.il;
On Thu, 21 Feb 2019 15:41:02 PST (-0800), tr...@konsulko.com wrote:
On Wed, Feb 20, 2019 at 05:45:59AM +, Anup Patel wrote:
This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.
The patches are based upon latest U-Boot source tree
(git://git.denx.de/u-boot.git) at
-riscv64_smode_defconfig
index b012443370..8adc23f826 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
+CONFIG_SIFIVE_SERIAL=y
Reviewed-by: Palmer Dabbelt
(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+
+ _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
+ _sifive_serial_init(regs);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct uart_sifive *regs =
+ (st
On Wed, 21 Nov 2018 14:06:00 PST (-0800), lukas.a...@aisec.fraunhofer.de wrote:
Hi Palmer,
On Wed, 2018-11-21 at 08:28 -0800, Palmer Dabbelt wrote:
On Tue, 20 Nov 2018 19:41:10 PST (-0800), a...@brainfault.org wrote:
> This patch adds kconfig option RISCV_SMODE to run u-boot in
> S-mode
On Tue, 20 Nov 2018 19:41:10 PST (-0800), a...@brainfault.org wrote:
This patch adds kconfig option RISCV_SMODE to run u-boot in
S-mode. When this opition is enabled we use s CSRs instead
of m CSRs.
It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we
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