[U-Boot] [PATCH 05/27] m68k: Use asm-generic/io.h

Convert the m68k architecture to make use of the new asm-generic/io.h to provide address mapping functions. As the generic implementations are suitable for m68k this is primarily a matter of emoving code. Feedback from architecture maintainers is welcome. Signed-off-by: Paul Burton <paul.

[U-Boot] [PATCH 03/27] arm: Use asm-generic/io.h

-off-by: Paul Burton <paul.bur...@imgtec.com> Cc: Albert Aribaud <albert.u.b...@aribaud.net> --- arch/arm/include/asm/io.h | 30 +- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 5834

[U-Boot] [PATCH 02/27] arc: Use asm-generic/io.h

Convert the arc architecture to make use of the new asm-generic/io.h to provide address mapping functions. As the generic implementations are suitable for arc this is primarily a matter of removing code. Feedback from architecture maintainers is welcome. Signed-off-by: Paul Burton <paul.

[U-Boot] [PATCH 00/27] Clean up address mapping functions & CONFIG_SYS_SDRAM_BASE

code & all MIPS boards to provide a physical CONFIG_SYS_SDRAM_BASE, which typically is zero. Paul Burton (27): Provide a generic io.h & address mapping functions arc: Use asm-generic/io.h arm: Use asm-generic/io.h blackfin: Use asm-generic/io.h m68k: Use asm-generic/io.h mic

[U-Boot] [PATCH 01/27] Provide a generic io.h & address mapping functions

es in the series will do so. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Cc: Albert Aribaud <albert.u.b...@aribaud.net> Cc: Alexey Brodkin <alexey.brod...@synopsys.com> Cc: Alison Wang <alison.w...@freescale.com> Cc: Angelo Dureghello <ang...@sysam.it> Cc

Re: [U-Boot] [PATCH 14/23] gpio: Provide dummy get/request & is_valid functions

On Monday, 26 September 2016 18:35:25 BST Simon Glass wrote: > Hi Paul, > > On 26 September 2016 at 12:29, Paul Burton <paul.bur...@imgtec.com> wrote: > > Allow for drivers to make use of driver model GPIOs when they're enabled > > & available without need

Re: [U-Boot] [PATCH] serial: ns16550: Fix serial output on Tegra186

On Friday, 30 September 2016 17:53:38 BST Alexandre Courbot wrote: > On 09/30/2016 05:46 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > For Tegra186 there are currently no UART clocks wired up in device tree. > > This exposes a regression introduced in commit

Re: [U-Boot] [PATCH 0/9] Python 3.x support for patman & dtoc

On Monday, 26 September 2016 18:33:19 BST Simon Glass wrote: > Hi Paul, > > On 26 September 2016 at 08:30, Paul Burton <paul.bur...@imgtec.com> wrote: > > This series makes patman & dtoc run on python 3.x, which allows them to > > work without hacks on distri

[U-Boot] [PATCH v2 09/10] dtoc: Decode strings for struct.unpack on python 3.x

On python 3.x struct.unpack will complain if we provide it with a string since it expects to operate on a bytes object. In order to satisfy this requirement, encode the string to a bytes object when running on python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon

[U-Boot] [PATCH v2 10/10] dtoc: Make integer division python 3.x safe

division. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Glass <s...@chromium.org> --- Changes in v2: None tools/dtoc/dtoc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 12aa990..11050b6 100755

[U-Boot] [PATCH v2 08/10] dtoc: Use items() to iterate over dictionaries in python 3.x

for simplicity. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: - Just use items() for all python versions tools/dtoc/dtoc.py | 8 tools/dtoc/fdt_fallback.py | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/dtoc/dtoc.py b

[U-Boot] [PATCH v2 07/10] patman: Fix doctest StringIO import for python 3.x

In python 3.x StringIO is no longer a module, and the class can instead be found in the io module. Adjust the code in the doctest input to account for both. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: - New patch, need found by running --test. tools/

[U-Boot] [PATCH v2 06/10] patman: Use items() to iterate over dictionaries

for simplicity. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: - Just use items() for all python versions tools/patman/settings.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 3caf379..7ef0ab0

[U-Boot] [PATCH v2 05/10] patman: Decode stdout/stderr as utf8, be python 3.x safe

In python 3.x reading stdout or stdin will produce a bytestring rather than a string. Decode it in CommunicateFilter such that the rest of the code can continue to deal with strings. This works fine with python 2.x too. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Gl

[U-Boot] [PATCH v2 03/10] patman: Make exception handling python 3.x safe

Syntax for exception handling is a little more strict in python 3.x. Convert all uses to a form accepted by both python 2.x & python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Glass <s...@chromium.org> --- Changes in v2: None tools/patman/command

[U-Boot] [PATCH v2 02/10] patman: Make print statements python 3.x safe

In python 3.x, print must be used as a function call. Convert all print statements to the function call style, importing from __future__ where we print with no trailing newline or print to a file object. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Glass <s...@chr

[U-Boot] [PATCH v2 04/10] patman: Import 'configparser' lower case to be python 3.x safe

In python 3.x module names used in import statements are case sensitive, and the configparser module is named in all lower-case. Import it as such in order to avoid errors when running with python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Glass <s...@chr

[U-Boot] [PATCH v2 00/10] Python 3.x support for patman & dtoc

This series makes patman & dtoc run on python 3.x, which allows them to work without hacks on distributions where the python binary is python 3.x. All changes are made in a way that continue to work on python 2.x, so both tools should work on either major version of python. Paul Burton

[U-Boot] [PATCH v2 01/10] patman: Replace tabs with spaces

In preparation for running on python 3.x, which will refuse to run scripts which mix tabs & spaces for indentation, replace 2 tab characters present in series.py with spaces. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Acked-by: Simon Glass <s...@chromium.org> --- Cha

Re: [U-Boot] [PATCH 15/23] gpio: eg20t: Add driver for Intel EG20T GPIO controllers

On Monday, 26 September 2016 18:35:32 BST Simon Glass wrote: > > +enum { > > + REG_IEN = 0x00, > > + REG_ISTATUS = 0x04, > > + REG_IDISP = 0x08, > > + REG_ICLR= 0x0c, > > + REG_IMASK = 0x10, > > + REG_IMASKCLR= 0x14, > > +

[U-Boot] [PATCH 23/23] boston: Enable CONFIG_DISTRO_DEFAULTS in defconfigs

symbols selected. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- configs/boston32r2_defconfig | 7 +-- configs/boston32r2el_defconfig | 7 +-- configs/boston64r2_defconfig | 7 +-- configs/boston64r2el_defconfig | 7 +-- 4 files changed, 4 insertions(+), 24 deletions(

[U-Boot] [PATCH 21/23] boston: Enable Realtek ethernet PHY support

The ethernet PHY used on the MIPS Boston development board is a Realtek RTL8211E. Enable support for it. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- include/configs/boston.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/boston.h b/include/configs/bo

[U-Boot] [PATCH 22/23] boston: Probe ethernet controller during boot

umeration step. Enable the GPIO driver to provide the PHY reset GPIO. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/Kconfig | 1 + arch/mips/dts/img,boston.dts | 6 +++--- configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/

[U-Boot] [PATCH 19/23] boston: Setup memory ranges in FDT provided to Linux

The boston memory map isn't suited to the simple "all memory starting from 0" approach that the MIPS arch_fixup_fdt() implementation takes. Instead we need to indicate the first 256MiB of DDR from 0 and the rest from 0x9000. Implement ft_board_setup to do that. Signed-off-by: P

[U-Boot] [PATCH 18/23] boston: Move CM GCRs away from flash

Move the MIPS Coherence Manager (CM) Global Configuration Registers (GCRs) away from the region of the physical address space which the Boston board's parallel flash is found in, such that we can access all of flash without clobbering GCRs. Signed-off-by: Paul Burton <paul.bur...@imgtec.

[U-Boot] [PATCH 20/23] boston: Bump CONFIG_SYS_BOOTM_LEN to 64MiB

The default value of CONFIG_SYS_BOOTM_LEN is too small for typical boston Linux kernels. Increase the limit to 64MB, which covers current kernels with plenty of breathing room. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- include/configs/boston.h | 1 + 1 file changed, 1 ins

[U-Boot] [PATCH 14/23] gpio: Provide dummy get/request & is_valid functions

g to perform such checks themselves. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- include/asm-generic/gpio.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 4aa0004..f6593a7 10

[U-Boot] [PATCH 17/23] MIPS: Make CM GCR base configurable

Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow defconfigs to set it. Provide the prompt in order to allow for that. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arc

[U-Boot] [PATCH 15/23] gpio: eg20t: Add driver for Intel EG20T GPIO controllers

Add a driver for the GPIO controller found in the Intel EG20T Platform Controller Hub. This is used on the MIPS Boston development board to provide GPIOs including ethernet PHY reset. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/gpio/Kconfig | 8 +++ driver

[U-Boot] [PATCH 16/23] net: pch_gbe: Support PHY reset GPIOs

Add support to the pch_gbe driver for resetting the PHY using a GPIO specified in the device tree. This matches the support already in Linux. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/net/pch_gbe.c | 29 +++-- drivers/net/pch_gbe.h | 1 + 2

[U-Boot] [PATCH 13/23] net: pch_gbe: Add cache maintenance

-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/net/pch_gbe.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 1432351..8866f66 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -120,6 +120,8 @@ stati

[U-Boot] [PATCH 12/23] net: pch_gbe: CPU accessible addresses are virtual

ses directly caused problems as they're in the user segment which would be mapped via the uninitialised TLB. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/net/pch_gbe.c | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/p

[U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

available to the PCI bus. Fix this by disabling that 1MB alignment, which allows all of the EG20T peripheral devices to be assigned memory space within the 1MB region available. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- configs/boston32r2_defconfig | 1 + configs/boston32r2el_def

[U-Boot] [PATCH 11/23] net: pch_gbe: Fix rx descriptor buffer addresses

The loop to set up buffer addresses in rx descriptors always operated on descriptor 0, rather than on each descriptor sequentially. Fix this in order to setup correct buffer addresses for each descriptor. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/net/pch_gbe.c | 4 +

[U-Boot] [PATCH 10/23] net: pch_gbe: Reset during probe

Using the EG20T gigabit ethernet controller on the MIPS Boston board, we find that we have to reset the controller in order for the RGMII link to the PHY to become functional. Without doing so we constantly time out in pch_gbe_mdio_ready. Signed-off-by: Paul Burton <paul.bur...@imgtec.

[U-Boot] [PATCH 08/23] pci: Make PCI bridge memory alignment configurable

that systems such as this can select an alignment which works for them. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/pci/Kconfig| 7 +++ drivers/pci/pci_auto.c | 24 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drive

[U-Boot] [PATCH 07/23] pci: Handle MIPS systems with virtual CONFIG_SYS_SDRAM_BASE

pproach to fixing this & converts CONFIG_SYS_SDRAM_BASE to a physical address for use by the PCI code when built for MIPS. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/pci/pci-uclass.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/p

[U-Boot] [PATCH 06/23] pci: Set of_offset for devices not probed via DT compatible strings

er binding a PCI device that wasn't already seen in the DT. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/pci/pci-uclass.c | 32 1 file changed, 32 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 3b00e6a

[U-Boot] [PATCH 05/23] pci: xilinx: Avoid writing memory base or limit registers

ar to me why this happens, and poking values from the shell doesn't seem to make anything clearer, but this workaround allows a MIPS Boston board to boot Linux & let Linux successfully probe the PCIe bus & all devices connected to it. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- dri

[U-Boot] [PATCH 04/23] pci: xilinx: Initialise the root bridge during probe

possible subordinate busses based upon the size of the ECAM region, and disable interrupts since U-Boot isn't using them. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/pci/pcie_xilinx.c | 36 ++-- 1 file changed, 34 insertions(+), 2 del

[U-Boot] [PATCH 03/23] MIPS: Fix map_physmem for cached mappings

pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 5b86386..ee7a592 100644 ---

[U-Boot] [PATCH 02/23] MIPS: Use ram_top, not bi_memsize, in arch_lmb_reserve

When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.bur...@imgtec.

[U-Boot] [PATCH 01/23] image: Use ram_top, not bi_memsize, in getenv_bootm_size

has 2GB of memory then the addition would wrap around to 0. The maximum amount of memory to be used by U-Boot is already accounted for by the ram_top field of struct global_data, so make use of that for the calculation instead. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- comm

[U-Boot] [PATCH 00/23] MIPS Boston fixes, ethernet support & cleanup

stem, the ethernet driver & the board code. With this series applied it is possible to load a Linux kernel image over ethernet on a MIPS Boston board & successfully boot it to a state where it can access the PCI devices in the system for itself. Paul Burton (23): image: Use ram_top, no

Re: [U-Boot] [PATCH 8/9] MIPS: add handling for generic and EJTAG exceptions

On Monday, 26 September 2016 19:41:22 BST Daniel Schwierzeck wrote: > 2016-09-26 12:29 GMT+02:00 Paul Burton <paul.bur...@imgtec.com>: > > Something I've had in the U-Boot source we use on Boston, Malta & SEAD-3 > > boards internally for a while is the ability to

[U-Boot] [PATCH 2/9] patman: Make print statements python 3.x safe

In python 3.x, print must be used as a function call. Convert all print statements to the function call style, importing from __future__ where we print with no trailing newline or print to a file object. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/patman/checkpatch.py

[U-Boot] [PATCH 0/9] Python 3.x support for patman & dtoc

This series makes patman & dtoc run on python 3.x, which allows them to work without hacks on distributions where the python binary is python 3.x. All changes are made in a way that continue to work on python 2.x, so both tools should work on either major version of python. Paul Burto

[U-Boot] [PATCH 9/9] dtoc: Make integer division python 3.x safe

division. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/dtoc/dtoc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 4ba8604..ac7ba6c 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -60,7 +60,7

[U-Boot] [PATCH 8/9] dtoc: Decode strings for struct.unpack on python 3.x

On python 3.x struct.unpack will complain if we provide it with a string since it expects to operate on a bytes object. In order to satisfy this requirement, encode the string to a bytes object when running on python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tool

[U-Boot] [PATCH 7/9] dtoc: Use items() to iterate over dictionaries in python 3.x

In python 3.x the iteritems() method has been removed from dictionaries, and the items() method does effectively the same thing. Convert the code to attempt to use iteritems() to be efficient on python 2.x, but use items() when that fails on python 3.x. Signed-off-by: Paul Burton <paul.

[U-Boot] [PATCH 6/9] patman: Use items() to iterate over dictionaries in python 3.x

In python 3.x the iteritems() method has been removed from dictionaries, and the items() method does effectively the same thing. Convert the code to attempt to use iteritems() to be efficient on python 2.x, but use items() when that fails on python 3.x. Signed-off-by: Paul Burton <paul.

[U-Boot] [PATCH 5/9] patman: Decode stdout/stderr as utf8, be python 3.x safe

In python 3.x reading stdout or stdin will produce a bytestring rather than a string. Decode it in CommunicateFilter such that the rest of the code can continue to deal with strings. This works fine with python 2.x too. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/

[U-Boot] [PATCH 4/9] patman: Import 'configparser' lower case to be python 3.x safe

In python 3.x module names used in import statements are case sensitive, and the configparser module is named in all lower-case. Import it as such in order to avoid errors when running with python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/patman/settings.

[U-Boot] [PATCH 1/9] patman: Replace tabs with spaces

In preparation for running on python 3.x, which will refuse to run scripts which mix tabs & spaces for indentation, replace 2 tab characters present in series.py with spaces. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/patman/series.py | 4 ++-- 1 file changed, 2

[U-Boot] [PATCH 3/9] patman: Make exception handling python 3.x safe

Syntax for exception handling is a little more strict in python 3.x. Convert all uses to a form accepted by both python 2.x & python 3.x. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- tools/patman/command.py | 2 +- tools/patman/cros_subprocess.py | 2 +- to

Re: [U-Boot] [PATCH 8/9] MIPS: add handling for generic and EJTAG exceptions

On Sunday, 25 September 2016 20:05:31 BST Daniel Schwierzeck wrote: > Add exception handlers for generic and EJTAG exceptions. Most of > the assembly code is imported from Linux kernel and adapted to U-Boot. > The exception vector table will be reserved above the stack before > U-Boot is

Re: [U-Boot] [PATCH v7 10/12] dm: syscon: Provide a generic syscon driver

On Thursday, 22 September 2016 22:15:48 BST Simon Glass wrote: > Hi, > > On 8 September 2016 at 00:47, Paul Burton <paul.bur...@imgtec.com> wrote: > > Provide a trivial syscon driver matching the generic "syscon" compatible > > string, allowing for simple

Re: [U-Boot] [PATCH v4] MIPS: Hang if run on a secondary CPU

On Wednesday, 21 September 2016 16:19:58 BST Daniel Schwierzeck wrote: > Am 21.09.2016 um 15:59 schrieb Paul Burton: > > Some systems are configured such that multiple CPUs begin running from > > their reset vector following a system reset. If this occurs then U-Boot > > wi

[U-Boot] [PATCH v4] MIPS: Hang if run on a secondary CPU

happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v4: - Presume Config5 is present for MIPSr6, as the arc

Re: [U-Boot] [PATCH v2] MIPS: Hang if run on a secondary CPU

On Wednesday, 21 September 2016 14:51:05 BST Matthew Fortune wrote: > Paul Burton <paul.bur...@imgtec.com> writes: > > Some systems are configured such that multiple CPUs begin running from > > their reset vector following a system reset. If this occurs then U-Boot > > w

[U-Boot] [PATCH] MIPS: Fix boston L2 cache Kconfig selection

The Kconfig entry for L2 cache support is MIPS_L2_CACHE, not MIPS_L2. Fix that. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Feel free to fold this into "boston: Introduce support for the MIPS Boston development board" as it's a minor fixup. arch/mips/Kconfig | 2 +-

Re: [U-Boot] [PATCH] MIPS: Hang if run on a secondary CPU

On Wednesday, 21 September 2016 15:14:41 BST Daniel Schwierzeck wrote: > Hi Paul, > > Am 21.09.2016 um 12:08 schrieb Paul Burton: > > Some systems are configured such that multiple CPUs begin running from > > their reset vector following a system reset. If this occurs then U

[U-Boot] [PATCH v2] MIPS: Hang if run on a secondary CPU

happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: - Rebase atop u-boot-mips/next - Execute a wait instruction in th

Re: [U-Boot] [PATCH] MIPS: Hang if run on a secondary CPU

On Wednesday, 21 September 2016 12:59:39 BST Langer, Thomas wrote: > Hello Paul, > > > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S > > index fc6dd66..dd37ac3 100644 > > --- a/arch/mips/cpu/start.S > > +++ b/arch/mips/cpu/start.S > > @@ -112,6 +112,31 @@ ENTRY(_start) > > > >

[U-Boot] [PATCH v3 14/14] MIPS: Ensure cache ops complete in mips_cache_reset

thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: - New patch Changes in v2: None arch/mips/lib/cache_init.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S ind

[U-Boot] [PATCH v3 13/14] MIPS: Clear hazard between TagLo writes & cache ops

Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <p

[U-Boot] [PATCH v3 12/14] MIPS: Ensure Config.K0=2 applies before any memory accesses

need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: - New patch Changes in v2: None

[U-Boot] [PATCH v3 11/14] MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Cha

[U-Boot] [PATCH v3 09/14] MIPS: L2 cache support

arly in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.bur...

[U-Boot] [PATCH v3 10/14] MIPS: Join the coherent domain when a CM is present

, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: - New patch Changes in v2: None arch/mips/include/asm/cm.h | 5 + arch/mips/lib/cache_init.S | 38 ++ 2 files c

[U-Boot] [PATCH v3 08/14] MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/Kconfig | 16

[U-Boot] [PATCH v3 07/14] MIPS: Define register names for cache init

Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/lib/ca

[U-Boot] [PATCH v3 06/14] MIPS: If we don't need DDR for cache init, init cache first

y faster. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/cpu/start.S | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6aec430..6f1d219 100644 --- a/arch/mips/cpu/start.S +

[U-Boot] [PATCH v3 03/14] MIPS: Probe cache line sizes once during boot

more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/cpu/cpu.c | 7 ++ arch/mips/include/asm/cache.h | 9

[U-Boot] [PATCH v3 05/14] MIPS: Preserve Config implementation-defined bits

MIPS architecture. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/cpu/start.S| 5 +++-- arch/mips/include/asm/mipsregs.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/start.S b/arc

[U-Boot] [PATCH v3 04/14] MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Bu

[U-Boot] [PATCH v3 02/14] MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init

In order to prepare for MIPS arch code making use of arch_cpu_init in a later patch, stop using it from ath79 SoC code & instead use the new mach_cpu_init which is provided for this purpose. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v3: None Changes in v2: - R

[U-Boot] [PATCH v3 01/14] board_f: Add a mach_cpu_init callback

new mach_cpu_init callback which is run immediately after arch_cpu_init. This will allow for architectures to have arch-wide code without needing individual machines to all implement their own arch_cpu_init with a call to some common function. Signed-off-by: Paul Burton <paul.bur...@img

[U-Boot] [PATCH v3 00/14] MIPS L2 cache support

DMA transfers. It also fixes up a few issues with the cache code in general, in particular ensuring that it clears execution hazards at appropriate points. Paul Burton (14): board_f: Add a mach_cpu_init callback MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init MIPS: Probe cache line s

[U-Boot] [PATCH] MIPS: Fix cache maintenance in relocate_code & simplify

erformed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off

[U-Boot] [PATCH] MIPS: Hang if run on a secondary CPU

happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/cpu/start.S| 25 + arch/mips/inclu

[U-Boot] [PATCH] image-fit: Fix fit_get_node_from_config semantics

is x86 code or is able to test it. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Cc: Jonathan Gray <j...@jsg.id.au> Cc: Marek Vasut <ma...@denx.de> --- common/image-fdt.c | 2 +- common/image-fit.c | 2 +- common/image.c | 2 +- 3 files changed, 3 insertions(+), 3

Re: [U-Boot] [PATCH] Repair image-fit: switch ENOLINK to ENOENT

that would seem to make sense but it would mean checking all the callers, direct or indirect, of fit_get_node_from_config to see whether they rely upon -ENOENT for the config not found case. Thanks, Paul > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Jonathan Gray <j...@js

[U-Boot] [PATCH] Revert "image-fit: switch ENOLINK to ENOENT"

mit to fix FIT image handling. This reverts commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT"). Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Cc: Jonathan Gray <j...@jsg.id.au> --- common/image-fit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) d

Re: [U-Boot] [PATCH v7 01/12] clk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabled

On 11/09/16 14:25, Masahiro Yamada wrote: > Hi Paul, > > 2016-09-09 17:01 GMT+09:00 Paul Burton <paul.bur...@imgtec.com>: >> On 09/09/16 04:15, Masahiro Yamada wrote: >>> 2016-09-08 15:47 GMT+09:00 Paul Burton <paul.bur...@imgtec.com>: >>

Re: [U-Boot] [PATCH v2 09/10] MIPS: L2 cache support

On 10/09/16 17:55, Daniel Schwierzeck wrote: > Am 09.09.2016 um 15:44 schrieb Paul Burton: >> This patch adds support for initialising & maintaining L2 caches on MIPS >> systems. The L2 cache configuration may be advertised through either >> coprocessor 0 or the MIPS Co

Re: [U-Boot] [PATCH v7 12/12] boston: Introduce support for the MIPS Boston development board

On 10/09/16 13:17, Daniel Schwierzeck wrote: > > > Am 08.09.2016 um 08:47 schrieb Paul Burton: >> This patch introduces support for building U-Boot to run on the MIPS >> Boston development board. This is a board built around an FPGA & an >> Intel EG20T Platfo

[U-Boot] [PATCH v2 06/10] MIPS: If we don't need DDR for cache init, init cache first

y faster. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/cpu/start.S | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6aec430..6f1d219 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mi

[U-Boot] [PATCH v2 10/10] MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Cha

[U-Boot] [PATCH v2 09/10] MIPS: L2 cache support

arly in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.bur...

[U-Boot] [PATCH v2 08/10] MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/Kconfig | 16 arch/mips/cpu/Ma

[U-Boot] [PATCH v2 07/10] MIPS: Define register names for cache init

Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/lib/cache_i

[U-Boot] [PATCH v2 04/10] MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Bu

[U-Boot] [PATCH v2 05/10] MIPS: Preserve Config implementation-defined bits

MIPS architecture. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/cpu/start.S| 5 +++-- arch/mips/include/asm/mipsregs.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S ind

[U-Boot] [PATCH v2 03/10] MIPS: Probe cache line sizes once during boot

more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/cpu/cpu.c | 7 ++ arch/mips/include/asm/cache.h | 9 arch/mips/i

[U-Boot] [PATCH v2 02/10] MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init

In order to prepare for MIPS arch code making use of arch_cpu_init in a later patch, stop using it from ath79 SoC code & instead use the new mach_cpu_init which is provided for this purpose. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: - Rebase atop changes

[U-Boot] [PATCH v2 01/10] board_f: Add a mach_cpu_init callback

new mach_cpu_init callback which is run immediately after arch_cpu_init. This will allow for architectures to have arch-wide code without needing individual machines to all implement their own arch_cpu_init with a call to some common function. Signed-off-by: Paul Burton <paul.bur...@img

[U-Boot] [PATCH v2 00/10] MIPS L2 cache support

DMA transfers. Paul Burton (10): board_f: Add a mach_cpu_init callback MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init MIPS: Probe cache line sizes once during boot MIPS: Enable use of the instruction cache earlier MIPS: Preserve Config implementation-defined bits MIPS: If we d

Re: [U-Boot] [PATCH v7 01/12] clk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabled

On 09/09/16 04:15, Masahiro Yamada wrote: > 2016-09-08 15:47 GMT+09:00 Paul Burton <paul.bur...@imgtec.com>: >> The implementations of clk_get_by_index & clk_get_by_name are only >> available when CONFIG_CLK is enabled. > > Unless I am missing something, > I

Re: [U-Boot] [PATCH 1/9] MIPS: Add arch-wide arch_cpu_init

On 08/09/16 11:47, Marek Vasut wrote: > On 09/08/2016 12:36 PM, Paul Burton wrote: >> On 08/09/16 11:02, Marek Vasut wrote: >>> On 09/07/2016 07:48 PM, Paul Burton wrote: >>>> Add an implementation of arch_cpu_init that covers all MIPS boards, in >>>>

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