Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

On 2/28/2017 8:38 PM, Rush, Jason A. wrote: [...] > > This also works. > > Marek - how do you feel about a patch series with the following: > > 1. revert commit 57897c13de03ac0136d64641a3eab526c6810387 > spi: cadence_qspi_apb: Use 32 bit indirect write transaction when > possible > 2.

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

On 2/25/2017 1:25 AM, Rush, Jason A. wrote: > R, Vignesh wrote: >> On 2/24/2017 12:55 AM, Marek Vasut wrote: >>> On 02/23/2017 08:22 PM, Rush, Jason A. wrote: >>>> Marek Vasut wrote: >>>>> On 02/22/2017 06:37 PM, Rush, Jason A. wrote: >>>>&

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

On 2/24/2017 12:55 AM, Marek Vasut wrote: > On 02/23/2017 08:22 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 02/22/2017 06:37 PM, Rush, Jason A. wrote: Marek Vasut wrote: > On 02/21/2017 05:50 PM, Rush, Jason A. wrote: [...] >> >> While I was debugging some of my changes, I

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

On 12/21/2016 10:42 AM, Vignesh R wrote: > According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC > TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit > data interface writes until the last word of an indirect transfer > otherwise indirect writes is known to

Re: [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation

[...] On 11/4/2016 4:31 PM, Jagan Teki wrote: >>> >> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c >>> >> index 52520dff6325..b5de70bf40e3 100644 >>> >> --- a/drivers/spi/ti_qspi.c >>> >> +++ b/drivers/spi/ti_qspi.c >>> >> @@ -16,6 +16,7 @@ >>> >> #include >>> >> #include >>> >>

Re: [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

On 10/31/2016 5:24 PM, Tom Rini wrote: > On Mon, Oct 31, 2016 at 09:40:34AM +0530, Vignesh R wrote: > >> Update the spi-max-frequency property of m25p80 flash slave to match >> that of TI QSPI controller node, so that QSPI operations happen at >> maximum supported frequency of 76.8MHz. >> >>

Re: [U-Boot] [PATCH 2/2] spi: ti_qspi: Fix baudrate divider calculation

On 10/14/2016 12:27 PM, Jagan Teki wrote: > On Fri, Oct 14, 2016 at 10:54 AM, Vignesh R wrote: ... DECLARE_GLOBAL_DATA_PTR; @@ -118,7 +119,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) if (!hz)

Re: [U-Boot] [PATCH 3/4] net: cpsw: Add support to drive gpios for ethernet to be functional

On 7/26/2016 12:26 PM, Wolfgang Denk wrote: > Dear "R, Vignesh", > > In message <a210f61e-bf51-a946-013c-dd98fd9a1...@ti.com> you wrote: >> >>>> @@ -1203,6 +1206,16 @@ static int cpsw_eth_ofdata_to_platdata(struct >&g

Re: [U-Boot] [PATCH 3/4] net: cpsw: Add support to drive gpios for ethernet to be functional

On 7/25/2016 7:08 PM, Tom Rini wrote: > On Mon, Jul 25, 2016 at 06:40:22PM +0530, Vignesh R wrote: > >> On DRA72 EVM, cpsw slaves may be muxed with other modules. This >> selection is controlled by a pcf gpio line. Add support for cpsw driver >> to acquire mode-gpios and select the appropriate

Re: [U-Boot] [PATCH 1/2] spi: ti_qspi: Fix failure on multiple READ_ID cmd

On 7/11/2016 12:05 PM, Jagan Teki wrote: > On 11 July 2016 at 11:00, Vignesh R wrote: >> Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value >> QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in >> ti_qspi_cs_deactivate(). Therefore CS is never

Re: [U-Boot] [PATCH v4] dm: core: implement dev_map_phsymem()

On 5/6/2016 9:00 PM, Jagan Teki wrote: > On 6 May 2016 at 09:28, Vignesh R wrote: >> This API helps to map physical register addresss pace of device to >> virtual address space easily. Its just a wrapper around map_physmem() >> with MAP_NOCACHE flag. >> >> Signed-off-by:

Re: [U-Boot] QSPI XIP boot on am437x

Hi Albert, Thanks for the response! On 11/10/2015 5:44 PM, Albert ARIBAUD wrote: > Hello Vignesh, > > On Tue, 10 Nov 2015 14:29:54 +0530, Vignesh R wrote: >> Hi, >> >> With commit 7ae8350f67eea("ti: armv7: Move SPL SDRAM init to the right >> place, drop unused

Re: [U-Boot] [U-Boot RESEND v2 09/10] spi: ti_qspi: Use DMA to read from qspi flash

On 8/17/2015 1:48 PM, Jagan Teki wrote: On 17 August 2015 at 13:29, Vignesh R vigne...@ti.com wrote: ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R vigne...@ti.com Reviewed-by: Jagan Teki

Re: [U-Boot] [PATCH 08/11] spi: ti_qspi: Use DMA to read from qspi flash

On 7/15/2015 12:32 AM, Tom Rini wrote: On Thu, Jul 09, 2015 at 12:10:03PM +0530, Vignesh R wrote: On 07/03/2015 05:12 PM, Tom Rini wrote: On Fri, Jul 03, 2015 at 04:46:10PM +0530, Vignesh R wrote: ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x

Re: [U-Boot] [PATCH 08/11] spi: ti_qspi: Use DMA to read from qspi flash

On 7/3/2015 5:12 PM, Tom Rini wrote: On Fri, Jul 03, 2015 at 04:46:10PM +0530, Vignesh R wrote: ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R vigne...@ti.com This ignores the feedback from

Re: [U-Boot] [PATCH 09/11] dma: ti-edma3: Add BIT(x) macro definition

On 7/3/2015 7:27 PM, Andy Pont wrote: Vignesh wrote... [snip] +#define BIT(x) (1 (x)) + Is this not something that would be better in a global header file somewhere rather than it starting a trend of a per-driver, per-arch, etc. definitions? I