[PATCH] spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR

When Falcon Mode is enabled on RISC-V, use CONFIG_VAL to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED. Signed-off-by: Randolph --- common/spl/spl_opensbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 8127ebc946

Re: [PATCH V4 2/2] configs: andes: add watchdog support fot andes ae350

On Wed, Jan 24, 2024 at 09:37:41AM +0100, Stefan Roese wrote: Hi Stefan, Thank you for testing and reviewing. I have checked the error message and the relationship to my patch. The reason for the failure has nothing to do with my patch. Could you kindly help me run the CI test again? Randolph

[PATCH V4 2/2] configs: andes: add watchdog support fot andes ae350

It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs

[PATCH V4 1/2] drivers: watchdog: add andes atcwdt200 support

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile| 1 + drivers/watchdog/atcwdt200_wdt.c | 220

[PATCH V4 3/3] configs: andes: add the fdt blob copy address for SPL

Add the address to which the FDT blob is to be moved. Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + 4 files changed, 4

[PATCH V4 2/3] spl: riscv: falcon: move fdt blob to specified address

In Falcon Boot mode, the fdt blob should be move to the RAM from kernel BSS section. To avoid being cleared by BSS initialisation. SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies. Signed-off-by: Randolph --- board/AndesTech/ae350/ae350.c | 25 - common/spl/Kconfig

[PATCH V4 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V

Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 158 + 1 file changed, 158 insertions(+) diff --git a/doc/develop/falc

[PATCH V4 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V

n enabling LOAD_FIT_OPENSBI_OS_BOOT - Add SPL_PAYLOAD_ARGS_ADDR to defconfig. This is the address that SPL copies into defconfig. Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy addre

[PATCH V3 2/2] configs: andes: add watchdog support fot andes ae350

It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs

[PATCH V3 1/2] drivers: watchdog: add andes atcwdt200 support

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile| 1 + drivers/watchdog/atcwdt200_wdt.c | 220

[PATCH V2 2/2] configs: andes: add watchdog support fot andes ae350

It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs

[PATCH V2 1/2] drivers: watchdog: add andes atcwdt200 support

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile| 1 + drivers/watchdog/atcwdt200_wdt.c | 220 +++ 3 files

[PATCH RESEND 2/2] configs: andes: add watchdog support fot andes ae350

It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs

[PATCH RESEND 1/2] drivers: watchdog: add andes atcwdt200 support

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile| 1 + drivers/watchdog/atcwdt200_wdt.c | 219 +++ 3 files

[PATCH V3] riscv: binman: fix the load field format

Using /bits/ 64 prefix for 64 bits address Signed-off-by: Randolph Reviewed-by: Simon Glass --- arch/riscv/dts/binman.dtsi | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8dc7b..9271de0ddf

[PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address

In Falcon Boot mode, the fdt blob should be move to the RAM from kernel BSS section. To avoid being cleared by BSS initialisation. SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies. Signed-off-by: Randolph --- board/AndesTech/ae350/ae350.c | 25 - common/spl/Kconfig

[PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to

Add the address where the FDT blob should be moved. Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + 4 files changed, 4

[PATCH V3 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V

Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 171 + 1 file changed, 171 insertions(+) diff --git a/doc/develop/falc

[PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V

Changes in v3: - Change by suggestions in falcon.rst - Move the board-related code to arch-specific code, its the issue when enabling LOAD_FIT_OPENSBI_OS_BOOT - Add SPL_PAYLOAD_ARGS_ADDR to defconfig. This is the address that SPL copies into defconfig. Randolph (3): doc: falcon: riscv

[PATCH V2] riscv: binman: fix the load field format

Using /bits/64 prefix for 64bits address Signed-off-by: Randolph --- arch/riscv/dts/binman.dtsi | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8dc7b..777b1309d0 100644 --- a/arch/riscv/dts

Re: [PATCH] riscv: binman: fix the load field format

Hi Simon, Thanks a lot. On Fri, Nov 10, 2023 at 04:50:24AM -0700, Simon Glass wrote: > Hi Randolph, > > On Wed, Nov 8, 2023, 20:15 Randolph wrote: > > > > The #address-cells is now equal to 2. The format of the load field for > > the Linux kernel doesn't match. >

[PATCH 1/2] drivers: watchdog: add andes atcwdt200 support

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile| 1 + drivers/watchdog/atcwdt200_wdt.c | 219 +++ 3 files

[PATCH 2/2] configs: andes: add watchdog support fot andes ae350

It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs

[PATCH] riscv: binman: fix the load field format

The #address-cells is now equal to 2. The format of the load field for the Linux kernel doesn't match. Signed-off-by: Randolph --- arch/riscv/dts/binman.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index

[PATCH V2] doc: falcon: riscv: Falcon Mode boot on RISC-V

Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 159 + 1 file changed, 159 insertions(+) diff --git a/doc/develop/falc

[PATCH] doc: falcon: riscv: Falcon Mode boot on RISC-V

Add documentation to introduce the Falcon Mode on RISC-V In this mode, boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 159 + 1 file changed, 159 insertions(+) diff --git a/doc/develop/falcon

Re: Falcon mode on RISC-V

On Thu, Oct 19, 2023 at 10:49:56PM +0200, Heinrich Schuchardt wrote: Hi Heinrich > Hello Randolph, > > I just saw your patches merged to enable Falcon mode on RISC-V using > CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT. I did not see any documentation update. > > Should information abou

[PATCH V2 7/7] riscv: spl: andes: Move the DTB in front of kernel

of the kernel can avoid this error. Signed-off-by: Randolph --- board/AndesTech/ae350/ae350.c | 25 + 1 file changed, 25 insertions(+) diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 1c2288b6ce..d78ee403e6 100644 --- a/board/AndesTech/ae350/ae350.c

[PATCH V2 6/7] andes: config: add riscv falcon mode for ae350 platform

Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs

[PATCH V2 4/7] Makefile: delete file *.itb when make clean

Delete the output file *.itb Signed-off-by: Randolph --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9d2e31e494..a7aa8c02a0 100644 --- a/Makefile +++ b/Makefile @@ -2165,7 +2165,7 @@ CLEAN_FILES += include/bmp_logo.h include

[PATCH V2 5/7] spl: riscv: add os type for next booting stage

or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled. Signed-off-by: Randolph --- common/spl/spl_fit.c | 3 ++- common/spl/spl_opensbi.c | 9 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index ce6b8aa370..e9126f07f7 100644 --- a/common/spl/spl_fit.c +++ b

[PATCH V2 1/7] spl: riscv: opensbi: change the default os_type as varible

In order to introduce the Opensbi OS boot mode, the next stage boot image of OpenSBI should be configurable. Signed-off-by: Randolph Reviewed-by: Simon Glass --- common/spl/spl_opensbi.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/common/spl

[PATCH V2 3/7] riscv: dts: binman: add condition for opensbi os boot

Add condition for OpenSBI OS boot mode, by default it is not enabled. By default, binman creates the output file u-boot.itb. If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created after compilation instead of the default u-boot.itb. Signed-off-by: Randolph --- arch/riscv/dts/binman.dtsi

[PATCH V2 2/7] riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol

the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph --- arch/riscv/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 183885ebe7..49b6e1a4d6 100644

[PATCH V2 0/7] riscv: spl: OpenSBI OS boot mode

put file when make clean. Randolph (7): spl: riscv: opensbi: change the default os_type as varible riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol riscv: dts: binman: add condition for opensbi os boot Makefile: delete file *.itb when make clean spl: riscv: add os type for

[PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy

Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph --- arch/riscv

[PATCH RESEND 7/7] riscv: spl: andes: Move the DTB in front of kernel

of the kernel can avoid this error. Signed-off-by: Randolph --- board/AndesTech/ae350/ae350.c | 25 + 1 file changed, 25 insertions(+) diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 1c2288b6ce..d78ee403e6 100644 --- a/board/AndesTech/ae350/ae350.c

[PATCH RESEND 6/7] andes: config: add riscv falcon mode for ae350 platform

Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs

[PATCH RESEND 5/7] spl: riscv: add os type for next booting stage

or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled. Signed-off-by: Randolph --- common/spl/spl_fit.c | 4 common/spl/spl_opensbi.c | 7 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 730639f756..750562721a 100644 --- a/common/spl/spl_fit.c +++ b

[PATCH RESEND 4/7] riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol

the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. When SPL_OPENSBI_OS_BOOT is enabled, it will change the default FIT configure file "binman.dtsi" to "binman_linux.dtsi" Default is not enabled. Signed-off-by: Rando

[PATCH RESEND 3/7] spl: riscv: opensbi: change the default os_type as varible

In order to introduce the Opensbi OS boot mode, the next stage boot image of OpenSBI should be configurable. Signed-off-by: Randolph --- common/spl/spl_opensbi.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/common/spl/spl_opensbi.c b/common

[PATCH RESEND 2/7] riscv: dts: add binman_linux.dtsi for opensbi os boot mode

lename should be called "Image", which is located in linux/arch/riscv/boot. Signed-off-by: Randolph --- arch/riscv/dts/binman_linux.dtsi | 79 1 file changed, 79 insertions(+) create mode 100644 arch/riscv/dts/binman_linux.dtsi diff --git a/arch/risc

[PATCH RESEND 1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol

Introduce common Kconfig symbol for riscv architecture This symbol SPL_LOAD_FIT_CONFIG for binman itb layout selection Default is using binman.dtsi Signed-off-by: Randolph --- arch/riscv/Kconfig | 7 +++ arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_32.dts

[PATCH RESEND 0/7] riscv: spl: OpenSBI OS boot mode

enSBI OS boot mode. The Linux kernel image will also need to be provided for the generation of the FIT file. Randolph (7): riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: dts: add binman_linux.dtsi for opensbi os boot mode spl: riscv: opensbi: change the default os_type as varible ris

[PATCH 7/7] riscv: spl: andes: Move the DTB in front of kernel

of the kernel can avoid this error. Signed-off-by: Randolph --- board/AndesTech/ae350/ae350.c | 25 + 1 file changed, 25 insertions(+) diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 1c2288b6ce..d78ee403e6 100644 --- a/board/AndesTech/ae350/ae350.c

[PATCH 6/7] andes: config: add riscv falcon mode for ae350 platform

Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs

[PATCH 5/7] spl: riscv: add os type for next booting stage

or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled. Signed-off-by: Randolph --- common/spl/spl_fit.c | 4 common/spl/spl_opensbi.c | 7 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 730639f756..750562721a 100644 --- a/common/spl/spl_fit.c +++ b

[PATCH 4/7] riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol

the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. When SPL_OPENSBI_OS_BOOT is enabled, it will change the default FIT configure file "binman.dtsi" to "binman_linux.dtsi" Default is not enabled. Signed-off-by: Rando

[PATCH 3/7] spl: riscv: opensbi: change the default os_type as varible

In order to introduce the Opensbi OS boot mode, the next stage boot image of OpenSBI should be configurable. Signed-off-by: Randolph --- common/spl/spl_opensbi.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/common/spl/spl_opensbi.c b/common

[PATCH 2/7] riscv: dts: add binman_linux.dtsi for opensbi os boot mode

lename should be called "Image", which is located in linux/arch/riscv/boot. Signed-off-by: Randolph --- arch/riscv/dts/binman_linux.dtsi | 79 1 file changed, 79 insertions(+) create mode 100644 arch/riscv/dts/binman_linux.dtsi diff --git a/arch/risc

[PATCH 1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol

Introduce common Kconfig symbol for riscv architecture This symbol SPL_LOAD_FIT_CONFIG for binman itb layout selection Default is using binman.dtsi Signed-off-by: Randolph --- arch/riscv/Kconfig | 7 +++ arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_32.dts

[PATCH 0/7] riscv: spl: OpenSBI OS boot mode

enSBI OS boot mode. The Linux kernel image will also need to be provided for the generation of the FIT file. Randolph (7): riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: dts: add binman_linux.dtsi for opensbi os boot mode spl: riscv: opensbi: change the default os_type as varible ris

[PATCH V3 2/2] configs: andes: rearrange SPL mode memory layout

Unify the memory layout for u-boot SPL mode Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS" Signed-off-by: Randolph --- configs/ae350_rv32_spl_defconfig | 7 --- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 7 --

[PATCH V3 1/2] configs: andes: add vender prefix for target name

Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph Reviewed-by: Tom Rini --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig| 2 +- configs/ae350_rv32_d

[PATCH V3 0/2] andes: rearrange defconfig and dts

Changes in v3: - Drop the "SPL config option for itb layout" patch Changes in v2: - Split the original patch into three smaller ones Randolph (2): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout arch/riscv/Kconfig

Re: [PATCH V2 3/3] dts: andes: add SPL config option for itb layout

Hi Tom, Tom Rini 於 2023年9月18日 週一 下午11:04寫道： > > On Mon, Sep 18, 2023 at 08:11:36PM +0800, Randolph wrote: > > > Add SPL_LOAD_FIT_CONFIG for binman itb layout selection > > > > Signed-off-by: Randolph > > --- > > arch/riscv/dts/ae350-u-boot.dtsi

[PATCH V2 3/3] dts: andes: add SPL config option for itb layout

Add SPL_LOAD_FIT_CONFIG for binman itb layout selection Signed-off-by: Randolph --- arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_32.dts | 1 - arch/riscv/dts/ae350_64.dts | 1 - board/AndesTech/ae350/Kconfig| 6 ++ configs/ae350_rv32_defconfig

[PATCH V2 2/3] configs: andes: rearrange SPL mode memory layout

Unify the memory layout for u-boot SPL mode Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS" Signed-off-by: Randolph --- configs/ae350_rv32_spl_defconfig | 7 --- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 7 --

[PATCH V2 1/3] configs: andes: add vender prefix for target name

Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig| 2 +- configs/ae350_rv32_defconfig

[PATCH V2 0/3] andes: rearrange defconfig and dts

Changes in v2: - Split the original patch into three smaller ones Randolph (3): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout dts: andes: add SPL config option for itb layout arch/riscv/Kconfig | 4 ++-- arch/riscv

[PATCH] andes: rearrange defconfig and dts and memory layout for SPL.

Modify "CONFIG_AE350" to "CONFIG_ANDES_AE350" Unify the memory layout for u-boot SPL. Signed-off-by: Randolph --- arch/riscv/Kconfig | 4 +- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_