On Mon, 15 Jul 2024, at 11:38 AM, Andre Przywara wrote:
> On Sun, 14 Jul 2024 20:20:44 +1200
> "Ryan Walklin" wrote:
>
> Hi Ryan,
>
> I consider the fact that the AXP209 and the AXP717 use the same I2C
> address a sheer coincidence, so would like to keep the code re
obj-$(CONFIG_AXP313_POWER) += axp313.o
> +obj-$(CONFIG_AXP717_POWER) += axp_spl.o
> obj-$(CONFIG_AXP809_POWER) += axp809.o
> obj-$(CONFIG_AXP818_POWER) += axp818.o
> endif
> --
> 2.25.1
Tested with RG35XX-H and RG35XX-Plus boards (Allwinner H700 with AXP717).
Confirmed both DCDC2 and DCDC3 are set correctly in SPL, allowing successful
DRAM init and boot.
Tested-by: Ryan Walklin
Regards,
Ryan
d with an H700-based board and u-boot at the 512-sector/256KB offset.
Tested-by: Ryan Walklin
Regards,
Ryan
[AXP806_ID] = axp806_regulators,
> [AXP809_ID] = axp809_regulators,
> diff --git a/include/axp_pmic.h b/include/axp_pmic.h
> index aabafc8501b..ae62ef0d76d 100644
> --- a/include/axp_pmic.h
> +++ b/include/axp_pmic.h
> @@ -33,6 +33,7 @@ enum {
> AXP221_ID,
> AXP223_ID,
> AXP313_ID,
> + AXP717_ID,
> AXP803_ID,
> AXP806_ID,
> AXP809_ID,
> --
> 2.35.8
Confirmed working on H700 board with AXP717 PMIC and LPDDR4 DRAM controller
(Anbernic RG35XX-H). Registers and voltage ranges confirmed from datasheet.
Reviewed-by: Ryan Walklin
Regards,
Ryan
;
> +
> + return pmic_bus_setbits(AXP717_OUTPUT_CTRL1, 1U << (dcdc_num - 1));
> +}
> +
> +int axp_set_dcdc1(unsigned int mvolt)
> +{
> + return axp_set_dcdc(1, mvolt);
> +}
> +
> +int axp_set_dcdc2(unsigned int mvolt)
> +{
> + return axp_set_dcdc(2, mvolt);
> +}
&
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