Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
configs/sifive_fu540_defconfig | 2 ++
drivers/reset
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
drivers
boot-riscv/master.
V4:
-Rebased the series to u-boot/master.
V3:
-Add reset indexes in separate dt binding header instead of
updating the clock dt binding header which is synced from Linux
V2:
-Removed extra character in commit log of 2nd patch
V1:
-Base version.
Sagar Shrikant Kadam (5):
d
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
include/dt-bindings/reset/sifive-fu540
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
configs/sifive_fu540_defconfig | 2 ++
drivers/reset
V1:
-Base version.
Sagar Shrikant Kadam (5):
dt-bindings: prci: add indexes for reset signals available in prci
fu540: prci: use common reset indexes defined in binding header
fu540: dtsi: add reset producer and consumer entries
sifive: reset: add DM based reset driver for SiFive SoC's
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
include/dt-bindings/reset/sifive-fu540
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
drivers
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
configs/sifive_fu540_defconfig | 2 ++
drivers/reset
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/fu540
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/clk/sifive/fu540-prci.c | 17 +++--
1
/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv
updating the clock dt binding header which is synced from Linux
V2:
-Removed extra character in commit log of 2nd patch
V1:
-Base version.
Sagar Shrikant Kadam (5):
dt-bindings: prci: add indexes for reset signals available in prci
fu540: prci: use common reset indexes defined in bind
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
---
include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++
1 file changed, 19
L1 cache, MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Signed-off-by: Sagar Shrikant Kadam
Revie
so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
drivers/cpu/riscv_cpu.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/r
dc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/
0 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
drivers/cpu/cpu-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a
Hz: L1 cache, MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
=>
Sagar Shrikant Kadam (4):
riscv: dts: hifi
0 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/cpu-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpu/cpu-uclass.c b
L1 cache, MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Signed-off-by: Sagar Shrikant Kadam
Revie
so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/riscv_cpu.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 76b048
dc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Sagar Shrikant Kadam (4):
riscv: dts: hifive-unleashed-a00: add cpu aliases
uclass
dc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/
/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
configs/sifive_fu540_defconfig | 2 ++
drivers/reset
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/clock/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
drivers
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
==
V2:
-Removed extra character in commit log of 2nd patch
V1:
-Base version.
Sagar Shrikant Kadam (5):
dt-bindings: prci: add indexes for reset signals available in prci
fu540: prci: use common reset indexes defined in binding header
fu540: dtsi: add reset producer and consumer entries
s
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
include/dt-bindings/clock/sifive-fu540
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
include/dt-bindings/clock/sifive-fu540-prci.h | 8
1
reset dm driver and bind it within prci module.
Patch 5: Add Kconfig, Makefile entries and enable the driver
This series is based on mainline U-Boot
commit 2b8692bac1e8 ("Merge tag 'efi-2020-07-rc5-2' of
https://gitlab.denx.de/u-boot/custodians/u-boot-efi;)
Sagar Shrikant Kadam (5):
dt-bin
/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
arch/riscv/include/asm/arch-fu540/reset.h | 13
drivers
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/clock/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel [A
---
drivers/clk/sifive/fu540
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
configs/sifive_fu540_defconfig | 2 ++
drivers/reset/Kconfig | 9 +
drivers/reset
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
MMU
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/riscv_cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 8c4b5e7..ce722cb 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3
Add clk_request handler to check if a valid clock is requested.
Here clk_free handler is added for debug purpose which will display
details of clock passed to clk_free.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 21
99.100 MHz: MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: MMU
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/ri
u list
0: cpu@0 rv64imac
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
=>
Sagar Shrikant Kadam (4):
fu540: prci: add request and free clock handlers
riscv: dts: hifive-unleashed-a00: add cpu aliases
riscv: cpu: fixes to display proper CPU features
riscv: cpu: check and append L1 c
MMU
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/riscv_cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 8c4b5e7..ce722cb 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3
99.100 MHz: MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: MMU
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/cpu/ri
u list
0: cpu@0 rv64imac
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +
1 file changed, 5 inse
Add clk_request handler to check if a valid clock is requested,
Here clk_free handler is added for debug purpose which will display
details of clock passed to clk_free.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 21
tchwork.ozlabs.org/patch/1300369
[4] https://patchwork.ozlabs.org/patch/1300370
[5] https://patchwork.ozlabs.org/patch/1300373
All these together is available here:
https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v3
Sagar Shrikant Kadam (4):
fu540: prci: add request and free clock hand
ned-off-by: Sagar Shrikant Kadam
---
drivers/cpu/riscv_cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 8c4b5e7..ce722cb 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -35,6 +35,7 @@ static
99.100 MHz: MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: MMU
Signed-off-by: Sagar Shrikant Kadam
---
drivers/cpu/riscv_cpu.c | 4 +++-
1 file c
Add clk_request handler to check if a valid clock is requested,
Here clk_free handler is added for debug purpose which will display
details of clock passed to clk_free.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/clk/sifive/fu540-prci.c | 21 +
1 file changed, 21
u list
0: cpu@0 rv64imac
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/ris
gether is available here:
https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v2
Sagar Shrikant Kadam (4):
fu540: prci: add request and free clock handlers
riscv: dts: hifive-unleashed-a00: add cpu aliases
riscv: cpu: fixes to display proper CPU features
riscv: cpu: check and appe
re clock set in prci driver
if clock-frequency is not added to CPU nodes in device tree.
It is tested on HiFive Unleashed A00 board.
Signed-off-by: Sagar Shrikant Kadam
Tested-by: Vincent Chen
---
drivers/cpu/riscv_cpu.c | 39 ++-
1 file changed, 38 insertions(+),
Add handlers to check if a valid clock id is used to request clock
by any driver using clk_request/clk_free API calls.
Signed-off-by: Sagar Shrikant Kadam
Tested-by: Vincent Chen
---
drivers/clk/sifive/fu540-prci.c | 24
1 file changed, 24 insertions(+)
diff --git
ID = 3, freq = 999.100 MHz
3: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Sagar Shrikant Kadam (2):
fu540: prci: add request and free clock handlers
cpu: clk: riscv: populate proper CPU core clk frequency
drivers/clk/sifive/fu540-prci.c | 24 ++
Add fdt->gd info to bdinfo so that it is useful for debugging
and easily use it with fdt util.
Signed-off-by: Sagar Shrikant Kadam
---
cmd/bdinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175..96892b3 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinf
Shrikant Kadam
---
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index d7a6413..dae9f87 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u
Add the number of chip select information to spi nodes which
can be used by spi-uclass for error handling if invalid cs
number passed from command.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/fu540-c000.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/dts/fu540
.b 0x8060 0x8260 0x200
Total of 33554432 byte(s) were the same
=>--------
Sagar Shrikant Kadam (4):
fu540: dtsi: spi: add num-cs info to device tree
spi: fu540: add claim and release method to spi-sifive.c
dts: u-boot.dtsi: overri
Add missing bus claim/release method to spi driver for HiFive
Unleashed, and handle num_cs generously so that it generates
an error if invalid cs number is passed to sf probe.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/spi/spi-sifive.c | 36
1 file
Add fdt->gd info to bdinfo so that it is useful for debugging
and easily use it with fdt util.
Signed-off-by: Sagar Shrikant Kadam
---
cmd/bdinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175..96892b3 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinf
Add number of chip select information to spi nodes which
can be used by spi-uclass for error handling if invlaid cs
number passed from command.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/fu540-c000.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000
This patch adds a workaround to change the read/write opcodes
from QUAD to single bit mode. Idea here is to enable usage of
spi-flash on the board.
TODO:
-Enable QUAD mode for spi-flash on HiFive Unleashed A00 board.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/mtd/spi/spi-nor-core.c | 15
r = 2
Failed to initialize SPI flash at 0:2 (error -22)
=> sf probe 0:4
Invalid cs number = 4
Failed to initialize SPI flash at 0:4 (error -22)
=> sf probe 0:8
Invalid cs number = 8
Failed to initialize SPI flash at 0:8 (error -22)
=>
-by: Sagar Shrikant Kadam
---
board/sifive/fu540/Kconfig | 1 +
drivers/mtd/spi/sf_internal.h | 16 +++
drivers/mtd/spi/spi-nor-core.c | 63 --
drivers/mtd/spi/spi-nor-ids.c | 7 -
include/linux/mtd/spi-nor.h| 1 +
5 files changed, 85
to SNOR_PROTO_1_1_1 and fails.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/spi/spi-sifive.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index f990ad6..038fdb7 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers
Add missing bus claim/release method to spi driver for HiFive
Unleashed, and handle num_cs generously so that it generates
error if invalid cs number is passed to sf probe.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/spi/spi-sifive.c | 36
1 file changed
Include hifive-unleashed-a00-u-boot.dtsi introduced earlier
so that it gets compiled within the dt-blob.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/hifive-unleashed-a00.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts
b/arch/riscv/dts
Enable the DM based GPIO driver for FU540-C000 SoC.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/sifive/fu540/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5d65080
based gpio driver submitted
for review by Wesley W. Terpstra and/or Atish Patra
(many thanks !!). The linux driver can be referred
here [1]
[1]: https://lkml.org/lkml/2018/10/9/1103
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/include/asm/arch-generic/gpio.h | 35 ++
arch/riscv/include
erty
is not mentioned in device node.
-Check if gpio number passed from the command line is within the valid range.
Incorporated review comment from Bin Meng
-Renamed driver from fu540-gpio to sifive-gpio
-Include a proper header file
-Use dev->name as bank_name.
v0: Base version
Sagar Shrikan
Enable the DM based GPIO driver for FU540-C000 SoC.
Signed-off-by: Sagar Shrikant Kadam
---
board/sifive/fu540/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5d65080..5ca2147 100644
--- a/board/sifive/fu540/Kconfig
based gpio driver submitted
for review by Wesley W. Terpstra and/or Atish Patra
(many thanks !!). The linux driver can be referred
here [1]
[1]: https://lkml.org/lkml/2018/10/9/1103
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/include/asm/arch-generic/gpio.h | 35 +++
arch/riscv
f ngpio's property
is not mentioned in device node.
-Check if gpio number passed from the command line is within the valid range.
Incorporated review comment from Bin Meng
-Renamed driver from fu540-gpio to sifive-gpio
-Include a proper header file
-Use dev->name as bank_name.
v0: Base version
Sa
based gpio driver submitted
for review by Wesley W. Terpstra and/or Atish Patra
. The linux driver can be referred
here [1]
[1]: https://lkml.org/lkml/2018/10/9/1103
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/include/asm/arch-generic/gpio.h | 35 +++
arch/riscv/include/asm/gpio.h
pin as input
=>gpio input 3 #Configure gpio line 3 as input.
Sagar Shrikant Kadam (1):
gpio: fu540: add support for DM based gpio driver for FU540 SoC
arch/riscv/include/asm/arch-generic/gpio.h | 35 +++
arch/riscv/include/asm/gpio.h | 6 ++
board/sifiv
. For instance if spi-tx-bus-width and spi-rx-bus-width in the flash
device node in dt is set to 4 bit mode, the controller gets configured in
QUAD mode, whereas the spi nor scan tries to read the JEDEC ID with the
reg_proto set to SNOR_PROTO_1_1_1 and fails.
Signed-off-by: Sagar Shrikant Kadam
Add support for spi_nor_fixups similar to that done in linux.
Flash vendor specific fixups can be registered in spi_nor_ids.
and will be called after BFPT parsing to fix any wrong parameter
read from SFDP.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/mtd/spi/sf_internal.h | 5
is tested for plain SPI mode although it also supports QUAD
I/O mode.
Signed-off-by: Bhargav Shah
Signed-off-by: Sagar Shrikant Kadam
---
board/sifive/fu540/Kconfig | 5 +
drivers/mtd/spi/sf_internal.h | 18 +++
drivers/mtd/spi/spi-nor-core.c | 340
ash section is protected.
Sagar Shrikant Kadam (3):
spi: nor: add spi-nor-fixup handlers for nor devices
spi: nor: add support for is25wp256
spi: riscv: use single bit mode for spi transfers
board/sifive/fu540/Kconfig | 5 +
drivers/mtd/spi/sf_internal.h | 23 +++
drivers/mtd/
This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Anup Patel
---
board/sifive/fu540/fu540.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git
ial#
serial#=00d0
Change history against base patch:
V1:
-Reduced buf size by 2 bytes as suggested by Bin Meng.
-Used true as argument to WARN message instead of 1.
-Terminated the WARN message with newline.
Sagar Shrikant Kadam (1):
riscv: sifive: fu540: set serial environment variable from
This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.
Signed-off-by: Sagar Shrikant Kadam
---
board/sifive/fu540/fu540.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/board/sifive/fu540/fu540.c b
ial#
serial#=00d0
Sagar Shrikant Kadam (1):
riscv: sifive: fu540: set serial environment variable from otp
board/sifive/fu540/fu540.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
--
2.7.4
___
U-Boot mailing list
U-B
This patch aligns the current implementation of HiFive Unleashed
board configuration framework with the one described in doc/README.kconfig.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/Kconfig | 6 +-
arch/riscv/cpu/generic/Kconfig | 12
_unleashed .
-Update MAINTAINERS file with relevant entries corresponding to the above
changes.
This patch will conflict with few patches which are already submitted for
review,
it would be good if U-boot folks would suggest something accordingly.
Sagar Shrikant Kadam (1):
sifive: riscv: update Hifive
g bit for TSTC") available at[1]
[1] https://github.com/sifive/HiFive_U-Boot/tree/regression
Signed-off-by: Sagar Shrikant Kadam
---
drivers/serial/serial_sifive.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/serial/serial_sifive.c
phier-v2019.07'
of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier;).
Booted linux kernel uImage loaded over y-modem on the HiFive Unleashed A00
board.
Sagar Shrikant Kadam (1):
riscv : serial: use rx watermark to indicate rx data is present
drivers/serial/serial_sifive.c
Hi Anup,
Tested the entire V9 series with OpenSBI and mainline u-boot based
on commit fc6c0e29a28f6 ("Prepare v2019.07-rc4") along with few
Ramon Fried's patches present in your riscv_unleashed_clk_sync_v9 branch:
between commit fc6c0e29a28f6 ("Prepare v2019.07-rc4") and
commit 1a417ef71ce1
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