Hello,
What happened to this series? Has it been abandoned? Also, is it
possible to get memory size installed to the board dynamically?
Best regards,
Shengyu
在 2023/8/4 19:04, Macpaul Lin 写道:
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a
Sorry, seems this is a false warning as fdt_fixup_ethernet() would do this.
Best regards
在 2024/5/10 23:01, Shengyu Qu 写道:
Btw I didn't have a code path to pass the MAC address to kernel. So does
it actually exist?
Best regards,
Shengyu
在 2024/5/10 13:52, Heinrich Schuchardt 写道:
We already
在 2024/5/10 23:01, Shengyu Qu 写道:
Btw I didn't have a code path to pass the MAC address to kernel. So does
Typo, have->find
it actually exist?
Best regards,
Shengyu
OpenPGP_0xE3520CC91929C8E7.asc
Description: OpenPGP public key
OpenPGP_signature.asc
Description: OpenPGP digi
Btw I didn't have a code path to pass the MAC address to kernel. So does it
actually exist?
Best regards,
Shengyu
在 2024/5/10 13:52, Heinrich Schuchardt 写道:
We already support the VisionFive 2 and the Milk-V Mars board by
patching the VisionFive 2 device tree. With this patch the same
is done
LGTM.
Maintainers, please also apply this patch to 2024.04 branch when
accepting it.
Best regards,
Shengyu
The VisionFive 2 board supports saving the u-boot environment settings
are saved to on-board SPI flash. However the defconfig enables both
ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH,
Hello Leo,
This patch seems only landed in next branch, not master. It is seriously
needed to make visionfive 2 working properly. Could you merge it to
master branch?
Best regards,
Shengyu
Multiple revisions of the StarFive VisionFive 2 board exist. They can be
identified by reading their
Use fdt_fixup_memory to make the memory size data from dtb match
the actual size.
Signed-off-by: Shengyu Qu
Tested-by: Milan P. Stanić
---
board/starfive/visionfive2/starfive_visionfive2.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/starfive/visionfive2
Enable CONFIG_OF_BOARD_SETUP, so we could use ft_board_setup() to fixup
memory size passed to kernel.
Signed-off-by: Shengyu Qu
Tested-by: Milan P. Stanić
---
configs/starfive_visionfive2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/starfive_visionfive2_defconfig
b
are based on Jami's work and provide a fix for that.
[1]
https://patchwork.ozlabs.org/project/uboot/cover/20230911153253.20701-1-jamipkettu...@gmail.com/
Shengyu Qu (2):
configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP
board: visionfive2: Fixup memory size passed to kernel
board/starfive
Hello Jami,
I made a fix for memory size problem based on your series, but I can't try
that because I'm using 4GB version. Could you test this?
https://github.com/Headcrabed/u-boot/tree/ddr_fix_v1
Best regards,
Shengyu
From: Jami Kettunen
Currently booting a mainline Linux kernel via
Hello Jami,
For DDR size problem, I think we could enable CONFIG_OF_BOARD_SETUP, then use
ft_board_setup() to apply fdt_fixup_memory()? Just like what they did in spl.c:
https://patchwork.ozlabs.org/project/uboot/patch/20230615093652.23161-12-yanhong.w...@starfivetech.com/
Best regards,
Shengyu
SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by
default, but that's not need on JH7110, so disable that.
Signed-off-by: Shengyu Qu
---
configs/starfive_visionfive2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig
b
SPL_SYS_MALLOC_CLEAR_ON_INIT as default.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 8469ee7de5..e5549a01b8 100644
--- a/arch/riscv/cpu/jh7110
To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify
#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
Reviewed-by: Tom Rini
---
common/dlmalloc.c | 6 +++---
1 file changed, 3 insertions(+), 3
Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices
that need to clear ram before use to work correctly.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v5:
- Fix whitespace
---
Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git
:
- Revert v3's fix since original implementation is actually right
Changes since v4:
- Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
- Remove already merged patches
Changes since v5:
- Fix whitespace in patch 1
- Disable SYS_MALLOC_CLEAR_ON_INIT by default on Visionfive 2
Shengyu Qu (4
SPL_SYS_MALLOC_CLEAR_ON_INIT as default.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 8469ee7de5..e5549a01b8 100644
--- a/arch/riscv/cpu/jh7110
To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify
#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
common/dlmalloc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices
that need to clear ram before use to work correctly.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Kconfig b/Kconfig
index 91170bf8d2..588acbaf9b
:
- Revert v3's fix since original implementation is actually right
Changes since v4:
- Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
- Remove already merged patches
Shengyu Qu (3):
Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT
dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
riscv: cpu
Since PLDA PCIE driver is added and VL805 support is enabled in
defconfig for Starfive Visionfive 2, modify the document to keep
consistent.
Signed-off-by: Shengyu Qu
---
doc/board/starfive/visionfive2.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/doc/board/starfive/visionfive2.rst
Although PCIE driver already exists, board defconfig isn't configured to
enable PCIE enum on boot, thus USB storage device and NVME drive are not
supported by default. So modify defconfig to enable PCIE auto enum, then
start USB subsystem and scan nvme drive on boot.
Signed-off-by: Shengyu Qu
Since PLDA PCIE driver and dts already merged in upstream for JH7110,
add relative defconfig item for Starfive Visionfive 2 and make document
consist with actual code.
Shengyu Qu (2):
configs: starfive: Enable PCIE auto enum and NVME/USB stuff for
Starfive Visionfive 2
doc: board
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110
. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
Changes since v3:
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
Changes since v3:
- Revert v3's fix since original implementation is actually right
Shengyu Qu (3):
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
riscv: cpu: jh7110: Select
Hi Leo,
Seems you are right. I'll send v4 to fix this. Thank you.
Best regards,
Shengyu
Hi Shengyu,
On Tue, Aug 08, 2023 at 08:39:56PM +0800, Shengyu Qu wrote:
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing
On Starfive Visionfive 2, the u-boot environment settings are saved to
on-board SPI flash. Enable relative configs by default and set offset
and size according to upstream linux dts.
Signed-off-by: Shengyu Qu
---
configs/starfive_visionfive2_defconfig | 9 +
1 file changed, 9 insertions
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b
. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
---
arch/riscv/
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..6771d8d919 100644
v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
Shengyu Qu (3):
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
arch/riscv/Kconfig| 8
arch/riscv/cpu
. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/spl.c | 25 -
arch/riscv/cpu/start.S
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..6771d8d919 100644
into several patches
Shengyu Qu (3):
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
riscv: Add ZERO_MEM_BEFORE_USE implementation
riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
arch/riscv/Kconfig| 8
arch/riscv/cpu/jh7110/Kconfig | 1 +
arch/riscv/cpu/jh7110/spl.c | 25
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