On Tue, Aug 26, 2014 at 11:04:56AM -0600, Stephen Warren wrote:
On 08/26/2014 09:33 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Provide a new modifier to vsprintf() to print phys_addr_t variables to
avoid having to cast or #ifdef when printing them out. The %pa modifier
On Tue, Aug 26, 2014 at 05:14:17PM -0600, Simon Glass wrote:
Hi Thierry,
On 26 August 2014 09:33, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
Provide a new modifier to vsprintf() to print phys_addr_t variables to
avoid having to cast
On Wed, Aug 27, 2014 at 09:07:58AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 27.08.2014 08:21, schrieb Thierry Reding:
On Wed, Aug 27, 2014 at 07:21:51AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 26.08.2014 17:34, schrieb Thierry Reding:
From: Thierry Redingtred...@nvidia.com
On Wed, Aug 27, 2014 at 11:56:41AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 27.08.2014 10:51, schrieb Thierry Reding:
On Wed, Aug 27, 2014 at 09:07:58AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 27.08.2014 08:21, schrieb Thierry Reding:
On Wed, Aug 27, 2014 at 07:21:51AM +0200
On Tue, Aug 26, 2014 at 03:54:50PM +0300, Tuomas Tynkkynen wrote:
On 18/08/14 10:16, Thierry Reding wrote:
[...]
+static int as3722_gpio_direction_output(u8 gpio, u8 level)
+{
+ u8 value;
+ int err;
+
+ if (gpio 7)
+ return -EINVAL;
+
+ if (level == 0
On Wed, Aug 27, 2014 at 03:28:06PM +0200, Thierry Reding wrote:
On Tue, Aug 26, 2014 at 03:54:50PM +0300, Tuomas Tynkkynen wrote:
On 18/08/14 10:16, Thierry Reding wrote:
[...]
+static int as3722_gpio_direction_output(u8 gpio, u8 level)
+{
+ u8 value;
+ int err;
+
+ if (gpio
From: Thierry Reding tred...@nvidia.com
This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size is
mostly due to the large number of infrastructure that's added (libfdt, Tegra
specific drivers required by the PCIe driver). In this version I've included
all patches that were
From: Thierry Reding tred...@nvidia.com
Given a device tree node and a property name, the fdt_count_strings()
function counts the number of strings found in the property value.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include/libfdt.h| 9 +
lib/libfdt/fdt_ro.c | 20
From: Thierry Reding tred...@nvidia.com
Provide a new modifier to vsprintf() to print phys_addr_t variables to
avoid having to cast or #ifdef when printing them out. The %pa modifier
is used for this purpose, so phys_addr_t variables need to be passed by
reference, like so:
phys_addr_t
From: Thierry Reding tred...@nvidia.com
Given a device tree node and a property name, the new fdt_find_string()
function will look up a given string in the string list contained in the
property's value and return its index.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2
From: Thierry Reding tred...@nvidia.com
Given a device tree node, a property name and an index, the new function
fdt_get_string_index() will return in an output argument a pointer to
the index'th string in the property's value.
The fdt_get_string() is a shortcut for the above with the index
From: Thierry Reding tred...@nvidia.com
The fdtdec_pci_get_bdf() function returns the bus, device, function
triplet of a PCI device by parsing the reg property according to the
PCI device tree binding.
Acked-by: Simon Glass s...@chromium.org
Signed-off-by: Thierry Reding tred...@nvidia.com
From: Thierry Reding tred...@nvidia.com
The fdt_for_each_subnode() iterator macro provided by this patch can be
used to iterate over a device tree node's subnodes. At each iteration a
loop variable will be set to the next subnode.
Acked-by: Simon Glass s...@chromium.org
Signed-off-by: Thierry
From: Thierry Reding tred...@nvidia.com
This macro can be overridden in source files (before including common.h)
and can be used to specify a prefix for debug and error messages. An
example of how to use this is shown below:
#define pr_fmt(fmt) foo: fmt
#include common.h
From: Thierry Reding tred...@nvidia.com
When listing the devices on a PCI bus, the current code will blindly try
to access all devices. Internally this causes pci_bus_to_hose() to be
repeatedly called and output an error message every time. Prevent this
by calling pci_bus_to_hose() once and abort
From: Thierry Reding tred...@nvidia.com
i2c_bus_init() takes a bus number but relies on the currently selected
bus to determine which adapter to initialize. Make the function use the
bus passed in as parameter rather than the currently selected bus. While
at it, keep a pointer to the specified
From: Thierry Reding tred...@nvidia.com
When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.
This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception
From: Thierry Reding tred...@nvidia.com
This API operates on I2C adapters or I2C clients (a new type of object
that refers to a particular slave connected to an adapter). This is
useful to avoid having to call i2c_set_bus_num() whenever a device is
being accessed.
Drivers for I2C devices
From: Thierry Reding tred...@nvidia.com
This is useful to retrieve the U-Boot bus number of an I2C controller
given a device tree node.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/i2c/tegra_i2c.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/i2c
From: Thierry Reding tred...@nvidia.com
A subsequent patch will introduce a new API to access I2C adapters
directly rather than going through the bus number and constantly looking
up the same adapter. In order to share the adapter initialization code,
move it into a separate function and make
From: Thierry Reding tred...@nvidia.com
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Thierry Reding tred
From: Thierry Reding tred...@nvidia.com
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other
From: Thierry Reding tred...@nvidia.com
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/power/Makefile | 1 +
drivers/power/as3722.c | 300 +
include
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- wait for power-up/off operation to complete before returning
- document PCIE/VDEC mixup
From: Thierry Reding tred...@nvidia.com
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/dts/tegra124.dtsi | 10 ++
1 file changed, 10 insertions
From: Thierry Reding tred...@nvidia.com
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.
Tegra20
From: Thierry Reding tred...@nvidia.com
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.
This is based on the Linux
From: Thierry Reding tred...@nvidia.com
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- add missing interrupt-map-mask and interrupt-map properties
- include
From: Thierry Reding tred...@nvidia.com
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/dts/tegra124
From: Thierry Reding tred...@nvidia.com
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- add all regulators from Linux
From: Thierry Reding tred...@nvidia.com
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- include unit address in device tree node name
- add missing interrupt-map-mask and interrupt-map properties
arch
From: Thierry Reding tred...@nvidia.com
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.
Signed-off-by: Thierry Reding tred
From: Thierry Reding tred...@nvidia.com
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/dts/tegra30.dtsi | 9
From: Thierry Reding tred...@nvidia.com
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/dts/tegra124.dtsi | 67 ++
include/dt-bindings/clock
From: Thierry Reding tred...@nvidia.com
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Signed-off-by: Thierry Reding tred
From: Thierry Reding tred...@nvidia.com
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems
From: Thierry Reding tred...@nvidia.com
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off
From: Thierry Reding tred...@nvidia.com
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Signed-off-by: Thierry Reding tred
From: Thierry Reding tred...@nvidia.com
When DEBUG is set, output memory region used for malloc().
Signed-off-by: Thierry Reding tred...@nvidia.com
---
common/dlmalloc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index f9873393c183..3d6391e60acf
From: Thierry Reding tred...@nvidia.com
Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable declaration section to a separate line (rather than the
one with the opening brace) and keeps
From: Thierry Reding tred...@nvidia.com
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case
From: Thierry Reding tred...@nvidia.com
According to the top-level README file, this configuration setting can
be used to override the number of receive buffers that an ethernet NIC
uses.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/net/rtl8169.c | 6 +-
1 file changed, 5
From: Thierry Reding tred...@nvidia.com
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality
From: Thierry Reding tred...@nvidia.com
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected
From: Thierry Reding tred...@nvidia.com
Add the fdt_get_resource() and fdt_get_named_resource() functions which
can be used to parse resources (memory regions) from an FDT. A helper to
compute the size of a region is also provided.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes
From: Thierry Reding tred...@nvidia.com
This network interface card in found on the NVIDIA Jetson TK1.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/net/rtl8169.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 22ad70719937
From: Thierry Reding tred...@nvidia.com
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- if non
On Wed, Aug 27, 2014 at 06:52:16AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 26.08.2014 17:33, schrieb Thierry Reding:
From: Thierry Redingtred...@nvidia.com
i2c_bus_init() takes a bus number but relies on the currently selected
bus to determine which adapter to initialize. Make
On Sun, Aug 24, 2014 at 11:18:04PM +0200, Marcel Ziswiler wrote:
On Fri, 2014-08-22 at 13:31 -0600, Stephen Warren wrote:
+#define CONFIG_USE_ARCH_MEMCPY
That last option isn't set on other Tegra boards; what's it for?
This is my special gift to Thierry to leverage architecture
On Fri, Aug 22, 2014 at 09:03:49PM -0600, Simon Glass wrote:
Hi Thierry,
On 19 August 2014 07:06, Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Aug 19, 2014 at 06:52:22AM -0600, Simon Glass wrote:
Hi Theirry,
On 19 August 2014 04:59, Thierry Reding thierry.red...@gmail.com
On Fri, Aug 22, 2014 at 07:47:36PM -0600, Simon Glass wrote:
Hi Thierry,
On 22 August 2014 16:03, Thierry Reding thierry.red...@gmail.com wrote:
On Fri, Aug 22, 2014 at 02:12:19PM -0600, Simon Glass wrote:
On 22 August 2014 13:40, Thierry Reding thierry.red...@gmail.com wrote
Hi,
I've been running a couple of builds for a patch that I'm working on and
I noticed the following errors happening for all Exynos boards:
arch/arm/cpu/armv7/exynos/clock.c: In function 'clock_get_periph_rate':
arch/arm/cpu/armv7/exynos/clock.c:263:47: warning: array subscript
From: Thierry Reding tred...@nvidia.com
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio
On Wed, Aug 20, 2014 at 01:15:15PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
size is always non-negative, so it should be unsigned, whereas the
address and size can be larger than 32 bit on 64-bit architectures.
Change
On Wed, Aug 20, 2014 at 01:23:13PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
[...]
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+unsigned long noncached_alloc
On Wed, Aug 20, 2014 at 01:29:57PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so
On Wed, Aug 20, 2014 at 01:33:06PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached
On Wed, Aug 20, 2014 at 12:51:35PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller
On Wed, Aug 20, 2014 at 12:43:58PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
On Wed, Aug 20, 2014 at 12:20:20PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This reset is required for PCIe and the corresponding ID therefore needs
to be defined.
It might be worth mentioning in the commit
On Wed, Aug 20, 2014 at 12:24:11PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
diff --git a/arch/arm/cpu/tegra-common
On Wed, Aug 20, 2014 at 12:32:45PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control
On Wed, Aug 20, 2014 at 12:32:45PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
[...]
diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c
b/arch/arm/cpu/tegra124-common/xusb-padctl.c
+int fdtdec_count_strings(const void *fdt, int node, const char *prop_name
On Wed, Aug 20, 2014 at 12:38:15PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot
On Wed, Aug 20, 2014 at 12:39:14PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
On Wed, Aug 20, 2014 at 01:04:22PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
On Fri, Aug 22, 2014 at 01:27:57PM -0600, Simon Glass wrote:
On 22 August 2014 06:09, Thierry Reding thierry.red...@gmail.com wrote:
[...]
Note that I haven't turned the AS3722 support into a PMIC driver,
because the framework for that seems to be unusable. It doesn't seem to
abstract away
On Fri, Aug 22, 2014 at 11:33:39AM -0600, Stephen Warren wrote:
On 08/20/2014 01:04 PM, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root
On Fri, Aug 22, 2014 at 02:12:19PM -0600, Simon Glass wrote:
On 22 August 2014 13:40, Thierry Reding thierry.red...@gmail.com wrote:
[...]
I've opted instead to provide an somewhat higher-level API that users
can call to set voltages on the regulators and enable them.
But then this should
On Wed, Aug 20, 2014 at 01:12:20PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This series attempts to fix a long-standing problem in the rtl8169 driver
(though the same problem may exist in other drivers as well). Let me
On Wed, Aug 20, 2014 at 01:23:13PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Implement an API that can be used by drivers to allocate memory from a
poll that is mapped uncached. This is useful if drivers would otherwise
On Tue, Aug 19, 2014 at 03:28:09PM -0600, Simon Glass wrote:
Hi Thierry,
On 19 August 2014 07:12, Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Aug 19, 2014 at 06:55:18AM -0600, Simon Glass wrote:
On 19 August 2014 05:35, Thierry Reding thierry.red...@gmail.com wrote
On Tue, Aug 19, 2014 at 01:48:55PM +, Marcel Ziswiler wrote:
+ /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x31;
+
+ err = i2c_read(PMU_I2C_ADDRESS, addr, 1, data, 1);
You sure about that read?
Me wondering why it did not work on my shiny Apalis
On Wed, Aug 20, 2014 at 10:56:58AM +0200, Marcel Ziswiler wrote:
On Wed, 2014-08-20 at 08:38 +0200, Thierry Reding wrote:
Hehe... this should probably be i2c_write() instead. Perhaps this is on
by default on Beaver and Cardhu but not on the particular revision that
Apalis T30 uses?
Well
On Mon, Aug 18, 2014 at 01:01:17PM -0500, Joe Hershberger wrote:
Hi Thierry,
On Mon, Aug 18, 2014 at 1:45 AM, Thierry Reding thierry.red...@gmail.com
wrote:
From: Thierry Reding tred...@nvidia.com
It's not unusual for DHCP servers to take a couple hundred milliseconds
to respond
From: Thierry Reding tred...@nvidia.com
It's not unusual for DHCP servers to take a couple hundred milliseconds
to respond to DHCP discover messages. One possible reason for the delay
can be that the server checks (typically using an ARP request) that the
IP it's about to hand out isn't in use
From: Thierry Reding tred...@nvidia.com
When creating build directories also create parents as necessary. This
fixes a failure when building a hierarchical branch (i.e. foo/bar).
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- only create parent directories for the top
On Mon, Aug 18, 2014 at 11:52:36AM -0600, Simon Glass wrote:
Hi Thierry,
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
Given a device tree node, the fdt_n_addr_cells() function will walk up
the device tree and search
On Mon, Aug 18, 2014 at 11:58:09AM -0600, Simon Glass wrote:
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
[...]
+int fdt_get_string_index(const void *fdt, int node, const char *property,
+const char *string)
+{
+ const char *list
On Mon, Aug 18, 2014 at 12:06:26PM -0600, Simon Glass wrote:
Hi Thierry,
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
Add the fdt_get_resource() and fdt_get_named_resource() functions which
can be used to parse
On Mon, Aug 18, 2014 at 12:11:03PM -0600, Simon Glass wrote:
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
The fdt_for_each_subnode() iterator macro provided by this patch can be
used to iterate over a device tree node's
On Mon, Aug 18, 2014 at 12:24:06PM -0600, Simon Glass wrote:
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
This macro can be overridden in source files (before including common.h)
and can be used to specify a prefix
On Mon, Aug 18, 2014 at 12:37:46PM -0600, Simon Glass wrote:
Hi Thierry,
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port
On Tue, Aug 19, 2014 at 06:52:22AM -0600, Simon Glass wrote:
Hi Theirry,
On 19 August 2014 04:59, Thierry Reding thierry.red...@gmail.com wrote:
On Mon, Aug 18, 2014 at 11:52:36AM -0600, Simon Glass wrote:
Hi Thierry,
On 18 August 2014 01:16, Thierry Reding thierry.red
On Tue, Aug 19, 2014 at 06:55:18AM -0600, Simon Glass wrote:
On 19 August 2014 05:35, Thierry Reding thierry.red...@gmail.com wrote:
[...]
The Linux kernel handles this by wrapping it in an of_read_number()
helper and always returning u64, like this:
static inline u64
On Tue, Aug 19, 2014 at 06:57:54AM -0600, Simon Glass wrote:
Hi Thierry,
On 19 August 2014 06:22, Thierry Reding thierry.red...@gmail.com wrote:
On Mon, Aug 18, 2014 at 12:11:03PM -0600, Simon Glass wrote:
On 18 August 2014 01:16, Thierry Reding thierry.red...@gmail.com wrote:
From
On Tue, Aug 19, 2014 at 09:59:00AM -0600, Stephen Warren wrote:
On 08/19/2014 02:06 AM, Thierry Reding wrote:
On Mon, Aug 18, 2014 at 01:01:17PM -0500, Joe Hershberger wrote:
Hi Thierry,
On Mon, Aug 18, 2014 at 1:45 AM, Thierry Reding thierry.red...@gmail.com
wrote:
From: Thierry Reding
From: Thierry Reding tred...@nvidia.com
It's not unusual for DHCP servers to take a couple hundred milliseconds
to respond to DHCP discover messages. One possible reason for the delay
can be that the server checks (typically using an ARP request) that the
IP it's about to hand out isn't in use
From: Thierry Reding tred...@nvidia.com
When creating build directories also create parents as necessary. This
fixes a failure when building a hierarchical branch (i.e. foo/bar).
Signed-off-by: Thierry Reding tred...@nvidia.com
---
tools/buildman/builderthread.py | 2 +-
1 file changed, 1
From: Thierry Reding tred...@nvidia.com
Given a device tree node, the fdt_n_addr_cells() function will walk up
the device tree and search for an #address-cells property. It returns
the number of cells required by the device tree node to represent an
address.
Similarly the fdt_n_size_cells
From: Thierry Reding tred...@nvidia.com
Given a device tree node and a property name, the fdt_get_string_index()
function will look up a given string in the string list contained in the
property's value and return its index.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include/libfdt.h
From: Thierry Reding tred...@nvidia.com
This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size is
mostly due to the large number of infrastructure that's added (libfdt, Tegra
specific drivers required by the PCIe driver).
Patches 1-5 add various FDT helpers to make it easier
From: Thierry Reding tred...@nvidia.com
The fdtdec_pci_get_bdf() function returns the bus, device, function
triplet of a PCI device by parsing the reg property according to the
PCI device tree binding.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include/fdtdec.h | 11 +++
lib
From: Thierry Reding tred...@nvidia.com
The fdt_for_each_subnode() iterator macro provided by this patch can be
used to iterate over a device tree node's subnodes. At each iteration a
loop variable will be set to the next subnode.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include
From: Thierry Reding tred...@nvidia.com
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/tegra124
From: Thierry Reding tred...@nvidia.com
Add the fdt_get_resource() and fdt_get_named_resource() functions which
can be used to parse resources (memory regions) from an FDT. A helper to
compute the size of a region is also provided.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/tegra-common/Makefile | 1 +
arch/arm/cpu/tegra-common/powergate.c | 80
From: Thierry Reding tred...@nvidia.com
This macro can be overridden in source files (before including common.h)
and can be used to specify a prefix for debug and error messages. An
example of how to use this is shown below:
#define pr_fmt(fmt) foo: fmt
#include common.h
From: Thierry Reding tred...@nvidia.com
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/dts/tegra124.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/tegra124.dtsi b
From: Thierry Reding tred...@nvidia.com
This reset is required for PCIe and the corresponding ID therefore needs
to be defined.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/tegra20-common/clock.c | 4 ++--
arch/arm/cpu/tegra30-common/clock.c | 1
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