Re: [U-Boot] Regression in fastboot on X15 due to CDCE913 enabling

Hi Andrew, On 24/10/19 11:49 PM, Andrew F. Davis wrote: > On 10/24/19 11:25 AM, Vignesh Raghavendra wrote: >> Hi Sam, >> >> On 24-Oct-19 7:16 PM, Sam Protsenko wrote: >>> Putting Vignesh to "To:". >>> >>> Hi Vignesh, >>> >

Re: [U-Boot] [PATCH] usb: composite: add BOS descriptor support to composite framework

Hi Michal, On 14/10/19 6:22 PM, Michal Simek wrote: > From: T Karthik Reddy > > To add usb-3.0 support to peripheral device add BOS & SS capability > descriptors to gadget composite framework. > How was this patch tested? With what gadget function driver was this tested? I don't see *any*

Re: [U-Boot] Regression in fastboot on X15 due to CDCE913 enabling

Hi Sam, On 24-Oct-19 7:16 PM, Sam Protsenko wrote: > Putting Vignesh to "To:". > > Hi Vignesh, > > Please address Tero's comments below (I've marked with ^^^). Thanks. > > On Thu, Oct 24, 2019 at 3:54 PM Tero Kristo wrote: >> >> On 24/10/2019 13:32, Sam Protsenko wrote: >>> Hi Tero, >>> >>>

Re: [U-Boot] [PATCH 2/2] spi: cadence-qspi: Add direct mode support

On 18/10/19 6:12 PM, Simon Goldschmidt wrote: > On Fri, Oct 18, 2019 at 2:40 PM Vignesh Raghavendra wrote: >> >> Hi, >> >> On 18/10/19 2:34 PM, Simon Goldschmidt wrote: >>> On Thu, Oct 17, 2019 at 2:55 PM Simon Goldschmidt >>> wrote: >

Re: [U-Boot] [PATCH v2 3/6] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

Hi Stefan, On 23/10/19 8:06 AM, Stefan Roese wrote: > Hi Vignesh, > > On 10.10.19 07:52, Vignesh Raghavendra wrote: [...] >> + >> +    hbmc: hyperbus@47034000 { >> +    compatible = "ti,j721e-hbmc", "ti,am654-hbmc";

[U-Boot] [PATCH v3 6/6] configs: j721e_evm_a72_defconfig: Add HBMC related configs

Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot Signed-off-by: Vignesh Raghavendra --- v3: No change configs/j721e_evm_a72_defconfig | 12 1 file changed, 12 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6729e03620c8

[U-Boot] [PATCH v3 4/6] arm: dts: k3-j721e-som-p0: Add HyperFlash node

J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vignesh Raghavendra --- v3: No change arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch

[U-Boot] [PATCH v3 1/6] mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined

Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build error when CONFIG_SYS_MONITOR_BASE is not defined. Signed-off-by: Vignesh Raghavendra --- v3: No change v2: Make macro check consistent as pointed out by Stefan drivers/mtd/cfi_flash.c | 6 -- 1 file changed, 4

[U-Boot] [PATCH v3 5/6] configs: j721e_evm.h: Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT

Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks are automatically detected by CFI flash driver Signed-off-by: Vignesh Raghavendra --- v3: No change include/configs/j721e_evm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/j721e_evm.h b/include

[U-Boot] [PATCH v3 2/6] mtd: Add TI HyperBus Memory Controller driver

-off-by: Vignesh Raghavendra --- v3: No change v2: No change drivers/mtd/Kconfig | 7 +++ drivers/mtd/Makefile | 1 + drivers/mtd/hbmc-am654.c | 105 +++ 3 files changed, 113 insertions(+) create mode 100644 drivers/mtd/hbmc-am654.c diff --git

[U-Boot] [PATCH v3 0/6] J721e: Add HyperBus support

This series adds support for HyperBus Memory Controller of TI's J721e and AM654 SoCs. v3: Rebase onto latest master branch Vignesh Raghavendra (6): mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined mtd: Add TI HyperBus Memory Controller driver arm: dts: k3-j721e-mcu-wakeup: Add

[U-Boot] [PATCH v3 3/6] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

-by: Vignesh Raghavendra --- v3: Rebase onto latest master Increase functional clock frequency to 250MHz v2: No change arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 26 ++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3

Re: [U-Boot] [PATCH v3 3/3] spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry

Hi Jagan, On 23/10/19 12:00 AM, Jagan Teki wrote: > Hi Vignesh, > > On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra wrote: >> >> n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status >> register that indicates various errors that may be encoun

Re: [U-Boot] [PATCH 2/2] spi: cadence-qspi: Add direct mode support

Hi, On 18/10/19 2:34 PM, Simon Goldschmidt wrote: > On Thu, Oct 17, 2019 at 2:55 PM Simon Goldschmidt > wrote: >> >> On Thu, Oct 17, 2019 at 2:44 PM Vignesh Raghavendra wrote: >>> >>> Hi, >>> >>> On 17/10/19 5:09 PM, Simon Goldschmi

Re: [U-Boot] [PATCH v2 14/38] spi: Add support for memory-mapped flash

On 18/10/19 7:52 AM, Simon Glass wrote: > Hi, > > On Thu, 17 Oct 2019 at 08:28, Simon Glass wrote: >> >> Hi Vignesh, >> >> On Wed, 16 Oct 2019 at 04:28, Vignesh Raghavendra wrote: >>> >>> Hi Simon, >>> >>> On 12/10/19 10

Re: [U-Boot] [PATCH v2 14/38] spi: Add support for memory-mapped flash

Hi Simon, On 16/10/19 10:10 PM, Simon Glass wrote: > Hi Vignesh, > > On Wed, 16 Oct 2019 at 04:28, Vignesh Raghavendra wrote: >> >> Hi Simon, >> >> On 12/10/19 10:03 AM, Bin Meng wrote: >>> Hi Simon, >>> >>> On Sat, Oct 12, 2019 at 11:

Re: [U-Boot] [PATCH 2/2] spi: cadence-qspi: Add direct mode support

Hi, On 17/10/19 5:09 PM, Simon Goldschmidt wrote: > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote: >> >> Add support for Direct Access Controller mode of Cadence QSPI. This >> allows MMIO access to SPI NOR flash providing better read performance. >>

Re: [U-Boot] [PATCH 1/2] spi: cadence_qspi: Move to spi-mem framework

Hi Simon, On 17/10/19 4:50 PM, Simon Goldschmidt wrote: > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote: >> >> Current Cadence QSPI driver has few limitations. It assumes all read >> operations to be in Quad mode and thus does not support SFDP parsing. >> A

Re: [U-Boot] [PATCH v2] mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASH

DM_SPI_FLASH being used. > > Cc: Vignesh R > Signed-off-by: Jagan Teki > --- Acked-by: Vignesh Raghavendra > Changes for v2: > - use imply than select > > drivers/mtd/spi/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi/K

Re: [U-Boot] [PATCH] cmd: sf: Mark it default if DM_SPI_FLASH enabled

H. > > This would prevent explicit adding of CONFIG_CMD_SF when > DM_SPI_FLASH being enabled. > > Cc: Tom Rini > Cc: Vignesh Raghavendra > Signed-off-by: Jagan Teki > --- Acked-by: Vignesh Raghavendra > cmd/Kconfig | 1 + > 1 file changed, 1 insertion(+) >

Re: [U-Boot] [PATCH v2 14/38] spi: Add support for memory-mapped flash

Hi Simon, On 12/10/19 10:03 AM, Bin Meng wrote: > Hi Simon, > > On Sat, Oct 12, 2019 at 11:08 AM Simon Glass wrote: >> >> Hi Bin, >> >> On Wed, 9 Oct 2019 at 07:55, Bin Meng wrote: >>> >>> Hi Simon, >>> >>> On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote: On x86 platforms the SPI

Re: [U-Boot] [PATCH v2 0/6] J721e: Add HyperBus support

Hi Tom, On 10/10/19 11:22 AM, Vignesh Raghavendra wrote: > This series adds support for HyperBus Memory Controller of TI's J721e > and AM654 SoCs. > Stefan has provided Reviewed-bys for CFI related changes. Could you please pull in this series if there no further comments? Regard

[U-Boot] [PATCH 1/2] spi: cadence_qspi: Move to spi-mem framework

-by: Vignesh Raghavendra --- drivers/spi/cadence_qspi.c | 136 + drivers/spi/cadence_qspi.h | 9 +-- drivers/spi/cadence_qspi_apb.c | 124 -- 3 files changed, 91 insertions(+), 178 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b

[U-Boot] [PATCH 2/2] spi: cadence-qspi: Add direct mode support

Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Signed-off-by: Vignesh R Signed-off-by: Vignesh Raghavendra --- drivers/spi/cadence_qspi.c | 40 -- drivers/spi/cadence_qspi.h

[U-Boot] [PATCH 0/2] spi: cadence-qspi: Move to spi-mem APIs

that provide memory mapped access to flash. This greatly increases the read throughput. Tested with mt25qu512 flash and s25fl512 flash Simon, Would greatly appreciate if you could test this series on platforms that you have access to? Vignesh Raghavendra (2): spi: cadence_qspi: Move to spi-mem

[U-Boot] [PATCH] arm64: Add memcpy_{from, to}io() and memset_io() helpers

Provide optimized memcpy_{from,to}io() and memset_io(). This is required when moving large amount of data to and from IO regions such as IP registers or accessing memory mapped flashes. Code is borrowed from Linux Kernel v5.4. Signed-off-by: Vignesh Raghavendra --- arch/arm/include/asm/io.h

[U-Boot] [PATCH v3 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Reviewed-by: Simon Goldschmidt Tested-by: Simon

[U-Boot] [PATCH v3 2/3] spi-nor: spi-nor-ids: Add entries for mt25q variants

mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Tested-by: Simon Goldschmidt --- drivers/mtd/spi

[U-Boot] [PATCH v3 3/3] spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry

n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Reviewed-by: Simon

[U-Boot] [PATCH v3 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q*

* variants where missing Changes since v2: Add USE_FSR flags to all flash variants where missing Collect T-bys and R-bys Reword commit msgs as necessary Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a Vignesh Raghavendra (3): spi-nor: spi

[U-Boot] [PATCH v2 5/6] configs: j721e_evm.h: Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT

Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks are automatically detected by CFI flash driver Signed-off-by: Vignesh Raghavendra --- include/configs/j721e_evm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/j721e_evm.h b/include/configs

[U-Boot] [PATCH v2 4/6] arm: dts: k3-j721e-som-p0: Add HyperFlash node

J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e

[U-Boot] [PATCH v2 3/6] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 26 ++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index c217866e9a2b..8838771dc1a1 100644 --- a/arch/arm/dts/k3-j721e-mcu

[U-Boot] [PATCH v2 6/6] configs: j721e_evm_a72_defconfig: Add HBMC related configs

Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot Signed-off-by: Vignesh Raghavendra --- configs/j721e_evm_a72_defconfig | 12 1 file changed, 12 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 5cb933d87886..7ddf85fea743 100644

[U-Boot] [PATCH v2 1/6] mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined

Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build error when CONFIG_SYS_MONITOR_BASE is not defined. Signed-off-by: Vignesh Raghavendra --- v2: Make macro check consistent as pointed out by Stefan drivers/mtd/cfi_flash.c | 6 -- 1 file changed, 4 insertions(+), 2

[U-Boot] [PATCH v2 2/6] mtd: Add TI HyperBus Memory Controller driver

-off-by: Vignesh Raghavendra --- v2: No change drivers/mtd/Kconfig | 7 +++ drivers/mtd/Makefile | 1 + drivers/mtd/hbmc-am654.c | 105 +++ 3 files changed, 113 insertions(+) create mode 100644 drivers/mtd/hbmc-am654.c diff --git a/drivers/mtd

[U-Boot] [PATCH v2 0/6] J721e: Add HyperBus support

This series adds support for HyperBus Memory Controller of TI's J721e and AM654 SoCs. Vignesh Raghavendra (6): mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined mtd: Add TI HyperBus Memory Controller driver arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node arm: dts

Re: [U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser

On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote: > Hi, Vignesh, > > On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote: >> External E-Mail >> >> >> Hi Tudor, >> >> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote: >>> From:

Re: [U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser

Hi Tudor, On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote: > From: Tudor Ambarus > > JESD216 allow vendors to define their own SFDP tables. > > Add Microchip SFDP parser. The vendor table is allocated using > resource-managed kmalloc - the table will be freed on driver detach. > It will

Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*

gt;> I've check this patches on top of 31e086e460f. >> The read/write/erase seems to work. >> >> However, as I can see 'sf protect lock' doesn't work - it finish >> successfully but the area remains unlocked. > > Did you verify that area is indeed unlocked by writing data and t

Re: [U-Boot] [PATCH RFT v2 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Hi Simon, On 01/10/19 11:58 AM, Simon Goldschmidt wrote: > On Tue, Oct 1, 2019 at 6:58 AM wrote: >> >> >> >> On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote: >>> External E-Mail >>> >>> >>> Older variants of n25q256* and n25q512*

Re: [U-Boot] [PATCH 1/6] mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined

Hi Stefan, On 09/10/19 12:46 PM, Stefan Roese wrote: > Hi Vignesh, > > sorry for the late review. > > On 10.09.19 07:10, Vignesh Raghavendra wrote: >> Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build >> error when CONFIG_SYS_MONITOR_BASE is no

Re: [U-Boot] [PATCH 0/6] J721e: Add HyperBus support

Hi Stefan, On 10/09/19 10:40 AM, Vignesh Raghavendra wrote: > This series adds support for HyperBus Memory Controller of TI's J721e > and AM654 SoCs. > > Vignesh Raghavendra (6): > mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined > mtd: Add TI HyperBus Memory

[U-Boot] [PATCH 8/8] usb: gadget: Add gadget_is_cdns3() macro

Add a new bcdDevice entry for Cadence USB gadget controller similar to other controller and add gadget_is_cdns3() macro as well. Signed-off-by: Vignesh Raghavendra --- drivers/usb/gadget/gadget_chips.h | 8 1 file changed, 8 insertions(+) diff --git a/drivers/usb/gadget/gadget_chips.h

[U-Boot] [PATCH 7/8] usb: cdns3: Add TI wrapper driver for CDNS USB3 controller

Add driver to handle TI specific wrapper for Cadence USB3 controller present on J721e SoC. Based on Linux driver for the same. Signed-off-by: Vignesh Raghavendra --- drivers/usb/cdns3/Kconfig| 7 ++ drivers/usb/cdns3/Makefile | 2 + drivers/usb/cdns3/cdns3-ti.c | 193

[U-Boot] [PATCH 3/8] usb: gadget: Add match_ep() op to usb_gadget_ops

by the gadget controller driver Signed-off-by: Vignesh Raghavendra --- drivers/usb/gadget/epautoconf.c | 3 +++ include/linux/usb/gadget.h | 23 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index

[U-Boot] [PATCH 2/8] bitmaps: import for_each_set_bit() macro

Import for_each_set_bit() and associated macros and functions from Linux. This is useful in parsing interrupt registers and take action on each bit that is set. Signed-off-by: Vignesh Raghavendra --- include/linux/bitmap.h | 61 ++ 1 file changed, 61

[U-Boot] [PATCH 6/8] usb: cdns3: gadget: Implement udc_set_speed() callback

Implement udc_set_speed() callback to limit Controller's speed to high-speed/full-speed when working with gadgets that are high-speed or full-speed only Signed-off-by: Vignesh Raghavendra --- drivers/usb/cdns3/gadget.c | 30 ++ 1 file changed, 26 insertions(+), 4

[U-Boot] [PATCH 1/8] list: import list_first_entry_or_null()

Import list_first_entry_or_null() macro from Linux that would be used by Cadence USB driver Signed-off-by: Vignesh Raghavendra --- include/linux/list.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/linux/list.h b/include/linux/list.h index 5b8d1df5dfee

[U-Boot] [PATCH 4/8] usb: udc: Introduce ->udc_set_speed() method

that will just fail. So here introduce a new optional ->udc_set_speed() method which can be implemented by interested UDC drivers to achieve this purpose. Signed-off-by: Sherry Sun Signed-off-by: Vignesh Raghavendra --- drivers/usb/gadget/udc/udc-core.c | 23 +++ include/li

[U-Boot] [PATCH 0/8] usb: Add support for Cadence USB controller driver

: Introduce ->udc_set_speed() method Vignesh Raghavendra (7): list: import list_first_entry_or_null() bitmaps: import for_each_set_bit() macro usb: gadget: Add match_ep() op to usb_gadget_ops usb: Add Cadence USB3 host and gadget driver usb: cdns3: gadget: Implement udc_set_speed() callb

[U-Boot] [PATCH v2 3/3] spi-nor: spi-nor-ids: Add USE_FSR flag for mt25qu512a entry

mt25qu512a flash has Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag to the entry Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion

[U-Boot] [PATCH RFT v2 2/3] spi-nor: spi-nor-ids: Add entries for mt25q variants

Newer variants of mt25q* flashes support 4 Byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi

[U-Boot] [PATCH RFT v2 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Older variants of n25q256* and n25q512* do not support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[U-Boot] [PATCH RFT v2 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing

supports flag registers Tested on mt25qu512a variant Simon, Euginey, Could you test this patch series on your boards as well? Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable

[U-Boot] [PATCH 2/2] mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS

U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-core.c | 2 +- drivers/mtd/spi/spi-nor-ids.c | 2 +- 2 files changed, 2

[U-Boot] [PATCH 1/2] mtd: spi-nor-core: Use dev_err for reporting erase/write failures

Use dev_err() when reporting reason for erase/write failures so that users can be made aware of the reason for failure. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c

[U-Boot] [PATCH 0/2] spi-nor-core: Fix small sector erase with SFDP

First patch improves error reporting on erase/write failures Second patch makes sure small sector is used even when SFDP is enabled and CONFIG_SPI_FLASH_USE_4K_SECTORS is set. Jagan, Could you please consider these patches for next -rc? Vignesh Raghavendra (2): mtd: spi-nor-core: Use dev_err

Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Hi, On 25/09/19 4:37 PM, Simon Goldschmidt wrote: > On Tue, Sep 24, 2019 at 2:08 PM Simon Goldschmidt > wrote: >> [...] >>> >>> But, do you have access to n25q variants? And does that support 4 Byte >>> addressing opcode? What does its JEDEC ID read? >> >> No, at the moment I don't. I'll see if

Re: [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*

On 25/09/19 1:57 PM, Simon Goldschmidt wrote: > Hi Vignesh, > > On Wed, Sep 25, 2019 at 10:20 AM Vignesh Raghavendra wrote: >> >> Simon, >> >> On 24/09/19 5:54 PM, tudor.amba...@microchip.com wrote: >>> Hi, Simon, >>> >>> On 09/24/

Re: [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*

Simon, On 24/09/19 5:54 PM, tudor.amba...@microchip.com wrote: > Hi, Simon, > > On 09/24/2019 02:47 PM, Simon Goldschmidt wrote: >> External E-Mail >> >> >> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra wrote: >>> >>> Newer varia

Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*

me? Regards Vignesh > As I remember It worked with old u-boot spi-nor code, but I need to check it. > > --- > Eugeniy Paltsev > > > ________ > From: Vignesh Raghavendra > Sent: Tuesday, September 24, 2019 08:56 > To: Jagan Teki; Eu

Re: [U-Boot] Regressions in MTD / SPI FLASH

XS# sf write 0x8100 0x18 0x10 && echo OK > device 0 offset 0x18, size 0x10 > 06 | [0B -] [ret 0] > 02 00 18 00 00 | [16B out] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > [ret 0] > 05 | [1B in] 00 [ret 0] > 70 | [1B in] 81 [ret 0] > SF: 16 bytes @ 0x18 Wri

Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Simon, On 24-Sep-19 5:15 PM, Simon Goldschmidt wrote: > Hi Tudor, > > On Tue, Sep 24, 2019 at 1:36 PM wrote: >> [...] Simon, Could you provide dump of SFDP tables and all the 6 bytes READ ID of the flash that you have? >>> >>> I have a n251256a with JEDEC ID 20, ba, 19, 10,

Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*

On 24/09/19 2:13 PM, Simon Goldschmidt wrote: > HI Vignesh, > > On Tue, Sep 24, 2019 at 9:59 AM Vignesh Raghavendra wrote: >> >> Hi Simon, >> >> On 24/09/19 12:32 PM, Simon Goldschmidt wrote: >>> Hi Vignesh, >>> >>>

Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*

Hi Simon, On 24/09/19 12:32 PM, Simon Goldschmidt wrote: > Hi Vignesh, > > On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra wrote: >> >> This series removes SPI_NOR_4B_OPCODES flags from legacy variants of >> n25q256* and n25q512* and adds entries for newer v

[U-Boot] [PATCH RFT 2/3] spi-nor: spi-nor-ids: Rename mt25qu512a entry

mt25qu512a is just a rebranded name for n25q512a. All the 6 bytes of JEDEC ID bytes are same for mt25qu512a and n25q512a. Therefore rename mt25qu512a to "mt25qu512a (n25q512a)", so that its much clearer to user. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 2

[U-Boot] [PATCH RFT 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Older variants of n25q256* and n25q512* do not support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*

Newer variants of n25q256* and n25q512* flashes support 4 Byte addressing opcodes. Add entries for the same. These flashes Bit 6 set in 5th byte of READ ID response. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*

these patches and make sure 4 Byte opcodes are being used. (Probably by enabling/adding prints to cmd->opcode in spi_mem_exec_op() in drivers/spi/spi-mem.c Euginey, Could you test this series on top of latest u-boot master and confirm that your test cases still work? Regards Vignesh Vign

Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

eries fixing those entries. Regards Vignesh > Regards > Ashish >> >> Regards >> Vignesh >> >>> Still, so we have such an op-in possibility to enable 4 byte opcodes >>> on these chips? >>> >>> Regards, >>> Simon >

Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Hi Ashish, Simon, On 11/09/19 3:11 PM, Simon Goldschmidt wrote: > > > Ashish Kumar mailto:ashish.ku...@nxp.com>> > schrieb am Mi., 11. Sep. 2019, 10:49: > > > > > -Original Message- > > From: Vignesh Raghavendra mailto:vigne...@ti.co

[U-Boot] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes and there is no easy way to discover at runtime whether the flash supports this feature or not. Therefore don't set SPI_NOR_4B_OPCODES for these flashes. Signed-off-by: Vignesh Raghavendra For n25q512ax3

[U-Boot] [PATCH 1/2] spi-nor: spi-nor-ids: Merge "n25q512a" and "mt25qu512a" entries

either of them. With that we can have single entry for n25q512a and mt25qu512a. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-ids.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index a39

Re: [U-Boot] Regressions in MTD / SPI FLASH

probe" should be sufficient. Regards Vignesh On 10/09/19 5:24 PM, Vignesh Raghavendra wrote: > > > On 10/09/19 5:11 PM, Eugeniy Paltsev wrote: >> Hi Vignesh, >> >> that patch helps - both erase and write works fine. >> > > Thanks for testing! I

Re: [U-Boot] Regressions in MTD / SPI FLASH

: "Eugeniy Paltsev " > > --- > Eugeniy Paltsev > > > ____________ > From: Vignesh Raghavendra > Sent: Tuesday, September 10, 2019 08:07 > To: Eugeniy Paltsev; Jagan Teki > Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Alexey

[U-Boot] [PATCH 6/6] configs: j721e_evm_a72_defconfig: Add HBMC related configs

Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot Signed-off-by: Vignesh Raghavendra --- configs/j721e_evm_a72_defconfig | 12 1 file changed, 12 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 56df452fb6ca..ef91d07aa33f 100644

[U-Boot] [PATCH 2/6] mtd: Add TI HyperBus Memory Controller driver

-off-by: Vignesh Raghavendra --- drivers/mtd/Kconfig | 7 +++ drivers/mtd/Makefile | 1 + drivers/mtd/hbmc-am654.c | 105 +++ 3 files changed, 113 insertions(+) create mode 100644 drivers/mtd/hbmc-am654.c diff --git a/drivers/mtd/Kconfig b/drivers

[U-Boot] [PATCH 1/6] mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined

Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build error when CONFIG_SYS_MONITOR_BASE is not defined. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/cfi_flash.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd

[U-Boot] [PATCH 3/6] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 26 ++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 01a8f4a9908f..bb652f2fb8d4 100644 --- a/arch/arm/dts/k3-j721e-mcu

[U-Boot] [PATCH 4/6] arm: dts: k3-j721e-som-p0: Add HyperFlash node

J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e

[U-Boot] [PATCH 5/6] configs: j721e_evm.h: Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT

Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks are automatically detected by CFI flash driver Signed-off-by: Vignesh Raghavendra --- include/configs/j721e_evm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/j721e_evm.h b/include/configs

[U-Boot] [PATCH 0/6] J721e: Add HyperBus support

This series adds support for HyperBus Memory Controller of TI's J721e and AM654 SoCs. Vignesh Raghavendra (6): mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined mtd: Add TI HyperBus Memory Controller driver arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node arm: dts

Re: [U-Boot] Regressions in MTD / SPI FLASH

e failed and Read status/Read flag status register should have reported error values. Anyways, I guess I found a wrt how 4 Byte addressing is handled wrt n25q512* series. Could you try with below patch helps[1]? If not please provide logs similar what you have provide now. If below patch doe

Re: [U-Boot] [PATCH 07/10] ufs: Add glue layer driver for TI J721E devices

On 09/09/19 1:49 PM, Faiz Abbas wrote: > Add glue layer driver for the controller present on TI's J721E devices. > > Signed-off-by: Faiz Abbas > --- > drivers/ufs/Kconfig| 6 +++ > drivers/ufs/Makefile | 1 + > drivers/ufs/ti-j721e-ufs.c | 75

Re: [U-Boot] [PATCH 05/10] ufs: Add Initial Support for UFS subsystem

On 09/09/19 1:49 PM, Faiz Abbas wrote: > Add Support for UFS Host Controller Interface (UFSHCI) for communicating > with Universal Flash Storage (UFS) devices. The steps to initialize the > host controller interface are the following: > > - Initiate the Host Controller Initialization process by

Re: [U-Boot] [PATCH 02/10] scsi: Add max_bytes to scsi_platdata

On 09/09/19 1:49 PM, Faiz Abbas wrote: > diff --git a/include/scsi.h b/include/scsi.h > index 81ab43c842..076bdbc6a0 100644 > --- a/include/scsi.h > +++ b/include/scsi.h > @@ -168,6 +168,7 @@ struct scsi_platdata { > unsigned long base; > unsigned long max_lun; > unsigned long

Re: [U-Boot] Regressions in MTD / SPI FLASH

Hi, On 04/09/19 11:37 PM, Eugeniy Paltsev wrote: > We faced with regressions caused by > commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) > This switch was performed by removing entire u-boot spi-flash > core implementation and copying it from another project. > However the switch

Re: [U-Boot] [PATCH v4 2/4] USB: host: Add the USB3 host driver

Hi Sherry, [...] >> AFAIK, U-Boot does not support runtime switching of USB port to host from >> device and vice versa. This is the case for existing driver like DWC3/MUSB >> etc. >> >> Ideally we would need a role switch driver that unbinds and rebinds host vs >> device driver as when required

Re: [U-Boot] [PATCH v4 2/4] USB: host: Add the USB3 host driver

SB: >> >>     usbss0: cdns_usb@4104000 { >>         compatible = "ti,j721e-usb"; >>     [] >>         usb0: usb@600 { >>             compatible = "cdns,usb3-1.0.1"; >> >> The driver selection (host or device) could

[U-Boot] [PATCH] soc: ti: k3-navss-ringacc: fix k3_nav_ringacc_ring_reset_dma

In case dma_ring_reset_quirk is not set the k3_ringacc_ring_reset_dma will just exit without ring reset. Fix it, by adding ring reset call in case dma_ring_reset_quirk is not. Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh Raghavendra --- drivers/soc/ti/k3-navss-ringacc.c | 4 +++- 1

Re: [U-Boot] [PATCH v5 0/7] usb: Add cadence USB3 gadget/host/phy driver

Hi, On 28/08/19 7:52 PM, Sherry Sun wrote: > Hi Vignesh, [...] >> I see that Cadence USB driver for Linux kernel is still under development and >> DT compatible binding is supposed to be "cdns,usb3" not "cdns,usb3-1.0.0". >> See v11: >>

Re: [U-Boot] [PATCH v5 0/7] usb: Add cadence USB3 gadget/host/phy driver

Hi Sherry, On 21/08/19 8:05 PM, Sherry Sun wrote: > These patches introduce new Cadence driver to U-Boot. > The first patch is to add the Cadence USB3 IP(CDNS3) core and driver for > the usb gadget. > The second patch introduce the xhci-imx8 usb host driver separately. > The third patch

Re: [U-Boot] [EXT] Re: [Patch V3] drivers: mtd :spi: Enable 4B opcodes for SPANSION s25fl512s

>> s25fs512s and s25fl512s which has same JEDEC ID but only varies in >> operating volatge so s25fs512s shares same command set as >> mentioned >> below: >> – Serial Command subset and footprint compatible with S25FL-A, >> S25FL-K, S25FL-P, and S25FL-S SPI families – Multi I/O

Re: [U-Boot] [EXT] Re: [Patch V3] drivers: mtd :spi: Enable 4B opcodes for SPANSION s25fl512s

On 18/07/19 4:29 PM, Jagan Teki wrote: > On Thu, Jul 18, 2019 at 4:15 PM Ashish Kumar wrote: >> >> >> >>> -Original Message- >>> From: Jagan Teki >>> Sent: Thursday, July 18, 2019 3:59 PM >>> To: Ashish Kumar ; Vignesh R >>> Cc: U-Boot-Denx >>> Subject: [EXT] Re: [Patch V3] drivers:

Re: [U-Boot] [PATCH] spi: spi-mem: Fix read data size issue

On 10/07/19 2:53 PM, Ye Li wrote: > When slave drivers don't set the max_read_size, the spi-mem should directly > use data.nbytes and not limit to any size. But current logic will limit to > the max_write_size. > Indeed. Thanks for catching this! Acked-by: Vignesh Raghavendra

Re: [U-Boot] [PATCH v3 2/5] spi: add spi-mem driver for MediaTek MT7629 SoC

On 12/06/19 9:26 PM, Jagan Teki wrote: > + Vignesh > > On Tue, May 14, 2019 at 7:11 AM Weijie Gao wrote: >> >> This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR >> and SPI-NAND flashes. >> >> Cc: Jagan Teki >> Signed-off-by: Weijie Gao >> --- >> Changes since v1:

Re: [U-Boot] x86: SPI flash broken with SPI NOR

On 05/06/19 8:17 PM, Bin Meng wrote: > Hi Vignesh, > > On Wed, Jun 5, 2019 at 9:40 PM Bin Meng wrote: >> >> Hi Vignesh, >> >> On Sat, Apr 27, 2019 at 12:26 AM Vignesh Raghavendra wrote: >>> >>> Bin, >>> >>> On 26/04/19 7

Re: [U-Boot] [EXT] Re: [PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation

Hi Ashish, > Hi Vignesh > > Is this taken care now, plain text version was posted here > http://patchwork.ozlabs.org/patch/1090121/ > A similar patch[1] was proposed in meantime which has been merged to mainline U-Boot. So this issue must now be resolved. Let me know if the issue still

Re: [U-Boot] [PATCH 2/2] fsl_qspi: Improve QSPI driver to incorporate 4 byte commands

On 30/04/19 1:13 PM, Schrempf Frieder wrote: > Hi, > > On 26.04.19 06:58, Vignesh Raghavendra wrote: >> >> >> On 25/04/19 5:20 PM, Rajat Srivastava wrote: >>> >>> >>>> -Original Message- >>>> From: Vignesh Ragh

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