On Wed, Feb 8, 2017 at 5:35 PM, Yung-Ching LIN wrote:
> On Wed, Feb 8, 2017 at 10:47 AM, Joe Hershberger
> wrote:
>> On Wed, Feb 8, 2017 at 12:26 AM, Sekhar Nori wrote:
>>> On Wednesday 08 February 2017 12:36 AM, Yung-Ching LIN wrote:
>>>> On Tue, Feb 7, 201
On Wed, Feb 8, 2017 at 10:47 AM, Joe Hershberger
wrote:
> On Wed, Feb 8, 2017 at 12:26 AM, Sekhar Nori wrote:
>> On Wednesday 08 February 2017 12:36 AM, Yung-Ching LIN wrote:
>>> On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori wrote:
>>>> On Monday 06 Februar
On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori wrote:
> On Monday 06 February 2017 11:06 PM, Ken.Lin wrote:
>
The register setting would turn out to be 0x3D47 on our project boards and
>>> our signal measurement results show the patch (v2 version,
>>> https://patchwork.ozlabs.org/patch/723461/)
2017-02-02 10:01 GMT-08:00 Joe Hershberger :
> On Wed, Feb 1, 2017 at 1:55 PM, ken wrote:
>> Apply the previous setting for the reserved bits in SetDes Test and System
>> Mode Control register
>> to avoid the voltage peak issue while we do the IEEE PHY comformance test
>
> Seems reasonable. Was
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