Re: [U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10

On Tue, 6 Dec 2016, Chee Tien Fong wrote: > From: Tien Fong Chee > > The drivers is restructured such common functions, gen5 functions, > and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 > respectively. > > Signed-off-by: Tien Fong Chee

[U-Boot] [RFC PATCH] arm: socfpga: Update iomux and pll for c5 socdk RevE

From: Dinh Nguyen Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen --- Hi Marek, Without these pinmux and pll changes, DS-5 is unable to connect to my board and Linux is stuck in a

[U-Boot] [PATCH] arm: socfpga: clean up common config options

From: Dinh Nguyen Move common config options like these to socfpga_common.h: CONFIG_SYS_NO_FLASH CONFIG_DOS_PARTITION CONFIG_FAT_WRITE CONFIG_HW_WATCHDOG CONFIG_CMD_ASKENV CONFIG_CMD_BOOTZ CONFIG_CMD_CACHE CONFIG_CMD_DHCP CONFIG_CMD_EXT4 CONFIG_CMD_EXT4_WRITE

[U-Boot] [PATCHv2] usb: dwc2: disable erroneous overcurrent condition

From: Dinh Nguyen For the case where an external VBUS is used, we should enable the external VBUS comparator in the driver. This would prevent an unnecessary overcurrent error which would then disable the host port. The overcurrent condition was happening on the

[U-Boot] usb: dwc2: disable erroneous overcurrent condition

From: Dinh Nguyen For the case where an external VBUS is used, we should enable the external VBUS comparator in the driver. This would prevent an unnecessary overcurrent error which would then disable the host port. The overcurrent condition was happening on the

[U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew

From: Dinh Nguyen The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x(-420ps) to 0x(480ps),

[U-Boot] [PATCH 1/2] net: phy: micrel: add documentation for Micrel KSZ90x1 binding

From: Dinh Nguyen Add the DTS documentation for the Micrel KSZ90x1 binding. The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel] This takes the original document and adds a clarification on how the skew values

[U-Boot] [PATCH 2/3] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Dinh Nguyen There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file

[U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10

From: Dinh Nguyen Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen --- v2: Add commit

[U-Boot] [PATCHv2 3/3] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Dinh Nguyen On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to

[U-Boot] [PATCH 1/6] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Dinh Nguyen The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2

[U-Boot] [PATCH 6/6] arm: socfpga: arria10: remove board_init and s_init

From: Dinh Nguyen These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/socfpga.c | 17 - 1 file changed, 17 deletions(-) diff --git

[U-Boot] [PATCH 0/6] arm: socfpga: arria10: more a10 enablement

From: Dinh Nguyen Hi, This is another round of patches for the Arria10 device. There are still some build failures that related to the clocking, FPGA manager, and bridge support. Thanks, Dinh Nguyen (6): arm: socfpga: wrap system manager functions for A5/C5

[U-Boot] [PATCH 2/6] arm: socfpga: add reset manager defines for Arria10

From: Dinh Nguyen Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++ 1 file

[U-Boot] [PATCH 3/6] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Dinh Nguyen On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to

[U-Boot] [PATCH 5/6] arm: socfpga: arria10 fpga does not have bridges mapped

From: Dinh Nguyen On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/socfpga.c

[U-Boot] [PATCH 4/6] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Dinh Nguyen The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH] arm: socfpga: set the fpga global bit to disable HPS to FPGA signals

From: Dinh Nguyen We should be setting the FPGA Interface Group global bit that will correctly disable all interfaces between the FPGA and HPS. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 +- 1 file changed, 1 insertion(+), 1

[U-Boot] [PATCH] arm: socfpga: remove note to add CONFIG_USB_DWC2_REG_ADDR

From: Dinh Nguyen Now that the USB DWC2 probing is done from OF, remove this note to add CONFIG_USB_DWC2_REG_ADDR. Signed-off-by: Dinh Nguyen --- include/configs/socfpga_common.h | 7 --- 1 file changed, 7 deletions(-) diff

[U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift

From: Dinh Nguyen On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by:

[U-Boot] [PATCHv5 1/2] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- v5: rename the mod_reest on A10 to match those in gen5 v4: rename mod_reset names to be used by both gen5

[U-Boot] [PATCH] arm: socfpga: fix trivial header preprocessor for socfpga_common.h

From: Dinh Nguyen Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with __CONFIG_SOCFPGA_OMMON_H__ as the file is now called socfpga_common.h Signed-off-by: Dinh Nguyen --- include/configs/socfpga_common.h | 6 +++--- 1 file changed,

[U-Boot] [PATCHv4 0/9] ARM: socfpga: Add minimal support for Arria10

From: Dinh Nguyen Hi, This is v4 of the patch series that adds minimal support for Altera's Arria10 platform. v4: - s/CONFIG_SOCFPGA_GEN5/CONFIG_TARGET_SOCFPGA_GEN5 - rename mod_reset(s) in the gen5 reset manager to match a10 - clean up of #if-else throughout

[U-Boot] [PATCHv4 9/9] arm: socfpga: fix up a questionable macro for SDMMC

From: Dinh Nguyen Move the macro into the socfpga_dwmci_clksel(). Signed-off-by: Dinh Nguyen --- v2: add SYSMGR_SDMMC_DRVSEL_SHIFT s/SYSMGR_SDMMC_SMPSEL_SHIFT/SYSMGR_SDMMC_SMPLSEL_SHIFT ---

[U-Boot] [PATCHv4 8/9] arm: socfpga: remove building scan manager

From: Dinh Nguyen The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- v4: use

[U-Boot] [PATCHv4 3/9] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- v4: rename mod_reset names to be used by both gen5 and a10 v3: remove duplicate reset function use

[U-Boot] [PATCHv4 2/9] arm: socfpga: arria10: add system manager defines

From: Dinh Nguyen Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- v4: none v3: combine system_manager_a10.h into system_manager.h v2: clean up parenthesis ---

[U-Boot] [PATCHv4 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- v4: none v3: further clean up, remove extra defines, keep bare mininum options v2: clean up

[U-Boot] [PATCHv4 4/9] arm: socfpga: arria10: add misc functions for Arria10

From: Dinh Nguyen Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen --- v4: be consistent and use

[U-Boot] [PATCHv4 1/9] arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property

From: Dinh Nguyen In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV ||

[U-Boot] [PATCHv4 6/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- v4: none v3: align with u-boot-socfpga/master v2: none ---

[U-Boot] [PATCHv4 7/9] arm: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- v4: reorder ARRIA10 below ARRIA5 v3: none v2: none --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2

[U-Boot] [RFC] arm: socfpga: introduce SOCFPGA_GEN5 or SOCFPGA_GEN10

From: Dinh Nguyen Define SOCFPGA_GEN5 which applies to Arria5/Cyclone5 hardware, and SOCFPGA_GEN10 for Arria10 hardware. This would allow us to use the shorten define in the rest of code. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH] arm: socfpga: fix up a questionable macro for SDMMC

From: Dinh Nguyen Not sure what made this macro questionable, but edit the macro to be similar to what is used in Linux. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- 1 file changed,

[U-Boot] [PATCH] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Dinh Nguyen Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 4 1 file changed, 4 insertions(+) diff --git

[U-Boot] [PATCHv2 6/9] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Dinh Nguyen Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- v2: Cleaned up copyright --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 7

[U-Boot] [PATCHv2 8/9] arm: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- v2: none --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig

[U-Boot] [PATCHv2 7/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen --- v2: none --- configs/socfpga_arria10_defconfig | 11 +++ 1 file changed, 11 insertions(+) create

[U-Boot] [PATCHv2 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen --- v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h --- include/configs/socfpga_arria10_socdk.h | 157

[U-Boot] [PATCHv2 9/9] arm: socfpga: remove building scan manager

From: Dinh Nguyen The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/Makefile | 7 +-- 1 file

[U-Boot] [PATCHv2 0/9] ARM: socfpga: Add minimal support for Arria10

From: Dinh Nguyen Hi, This is v2 of the patch series that adds minimal support for Altera's Arria10 platform. v2: - Removes the need for a separate /mach-socfpga/arria10 directory - Tries to re-use alot of the Arria5/Cyclone5 code - Removes the usage of unions

[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- v2: integrate into a5/c5 reset manager --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 66

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

From: Dinh Nguyen Add miscellaneous functions(arch_early_init_r, print_cpuinfo, overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to

[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

From: Dinh Nguyen Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- v2: clean up parenthesis --- .../mach-socfpga/include/mach/system_manager_a10.h | 157 + 1 file changed, 157

[U-Boot] [PATCHv2 3/9] arm: socfpga: arria10: add sdram defines for Arria10

From: Dinh Nguyen Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen --- v2: Remove union bitfields --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 + 1 file

[U-Boot] [PATCHv3 1/9] arm: socfpga: introduce SOCFPGA_GEN5 config property

From: Dinh Nguyen In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV.

[U-Boot] [PATCHv3 0/9] ARM: socfpga: Add minimal support for Arria10

From: Dinh Nguyen Hi, This is v3 of the patch series that adds minimal support for Altera's Arria10 platform. v3: - Add CONFIG_SOCFPGA_GEN5 for building for Arria5 and Cyclone5 - Clean up socfpga_arria10_socdk - Add patch to remove the macro

[U-Boot] [PATCHv3 9/9] arm: socfpga: fix up a questionable macro for SDMMC

From: Dinh Nguyen Move the macro into the socfpga_dwmci_clksel(). Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 8 +--- drivers/mmc/socfpga_dw_mmc.c| 5 +++-- 2

[U-Boot] [PATCHv3 7/9] arm: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- v2: none --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig

[U-Boot] [PATCHv3 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen --- v3: further clean up, remove extra defines, keep bare mininum options v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h

[U-Boot] [PATCHv3 2/9] arm: socfpga: arria10: add system manager defines

From: Dinh Nguyen Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- v3: combine system_manager_a10.h into system_manager.h v2: clean up parenthesis --- .../arm/mach-socfpga/include/mach/system_manager.h | 122

[U-Boot] [PATCHv3 4/9] arm: socfpga: arria10: add misc functions for Arria10

From: Dinh Nguyen Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen --- v3:

[U-Boot] [PATCHv3 3/9] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- v3: remove duplicate reset function use CONFIG_SOCFPGA_GEN5 v2: integrate into a5/c5 reset manager ---

[U-Boot] [PATCHv3 8/9] arm: socfpga: remove building scan manager

From: Dinh Nguyen The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only. Signed-off-by: Dinh Nguyen --- v3: use CONFIG_SOCFPGA_GEN5 option for build ---

[U-Boot] [PATCHv3 6/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen --- v3: align with u-boot-socfpga/master v2: none --- configs/socfpga_arria10_defconfig | 16 1

[U-Boot] [PATCHv2 2/2] ARM: socfpga: rename the cyclone5 and arria5 base address file

From: Dinh Nguyen When adding support for the Arria10 platform, we're going to name the file base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h to be base_addr_ac5.h for the Arria5 and Cyclone5 platform. Suggested-by: Marek Vasut

[U-Boot] [PATCHv2 1/2] ARM: socfpga: arria10: add base address map for Arria10

From: Dinh Nguyen Add the base address map for Arria10. Signed-off-by: Dinh Nguyen Reviewed-by: Marek Vasut --- v2: renamed to base_addr_a10.h --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 45

[U-Boot] [PATCH 10/10] ARM: socfpga: arria10: add support for building Arria10

From: Dinh Nguyen Update Makefile to build Arria 10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/Makefile | 7 +-- arch/arm/mach-socfpga/arria10/Makefile | 7 +++ 2 files changed, 12 insertions(+), 2

[U-Boot] [PATCH 04/10] ARM: socfpga: arria10: add stub sdram init for Arria10

From: Dinh Nguyen For now, sdram_a10.c will only have sdram_init() function, but this will get populated in the near future with more functionality. Also add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCH 03/10] ARM: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/arria10/reset_manager_a10.c | 83 +++

[U-Boot] [PATCH 01/10] ARM: socfpga: arria10: add base address map for Arria10

From: Dinh Nguyen Add the base address map for Arria10. Signed-off-by: Dinh Nguyen --- .../include/mach/socfpga_a10_base_addrs.h | 45 ++ 1 file changed, 45 insertions(+) create mode 100644

[U-Boot] [PATCH 08/10] ARM: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen --- configs/socfpga_arria10_defconfig | 11 +++ 1 file changed, 11 insertions(+) create mode 100644

[U-Boot] [PATCH 09/10] ARM: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig

[U-Boot] [PATCH 06/10] ARM: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen --- include/configs/socfpga_arria10_socdk.h | 292 1 file changed, 292 insertions(+) create mode

[U-Boot] [PATCH 02/10] ARM: socfpga: arria10: add system manager defines

From: Dinh Nguyen Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- .../mach-socfpga/include/mach/system_manager_a10.h | 157 + 1 file changed, 157 insertions(+) create mode 100644

[U-Boot] [PATCH 07/10] ARM: socfpga: arria10: add board files for the Arria10 SoCDK

From: Dinh Nguyen Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 9 +

[U-Boot] [PATCH 00/10] ARM: socfpga: Add minimal support for Arria10

From: Dinh Nguyen Hi, This patchset adds the foundation support for Arria10. The series builds for the Altera Arria10 SoCDK, but is not entirely functional on the hardware yet. This series really just add the defines, build and Kconfig layout for Arria10. There

[U-Boot] [PATCH] arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

From: Dinh Nguyen The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCHv2] arm: socfpga: enable data/inst prefetch and shared override in the L2

From: Dinh Nguyen Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared

[U-Boot] [PATCH 1/2] pl310: arm: fix up define typo for the share override bit

From: Dinh Nguyen s/L310_SHARED_ATT_OVERRIDE_ENABLE/PL310_SHARED_ATT_OVERRIDE_ENABLE Signed-off-by: Dinh Nguyen --- arch/arm/imx-common/cache.c | 2 +- arch/arm/include/asm/pl310.h | 2 +- 2 files changed, 2 insertions(+), 2

[U-Boot] [PATCH 2/2] arm: socfpga: enable data/inst prefetch and shared override in the L2

From: Dinh Nguyen Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared

[U-Boot] [PATCH] arm: dts: socfpga: add "u-boot, dm-pre-reloc" to socfpga_cyclone5_socdk dts

From: Dinh Nguyen We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in order for the SPL to use SD/MMC. Signed-off-by: Dinh Nguyen --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 3 +++ 1 file changed, 3

[U-Boot] [PATCHv3] arm: socfpga: Enable saveenv for SD/MMC

From: Dinh Nguyen Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- v3: Only define ENV_IS_NOWHERE if env is not in MMC, NAND, FAT, and SPI_FLASH v2: Move this option to be on a

[U-Boot] [PATCHv4] arm: socfpga: Enable saveenv for SD/MMC

From: Dinh Nguyen Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- v4: Move ENV_IS_NOWHERE to the mcvevk board config file v3: Only define ENV_IS_NOWHERE if env is not in MMC,

[U-Boot] [PATCH 2/3] arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk

From: Dinh Nguyen commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files" renames the configs files, so we should update the MAINTAINERS' entry. At the same time, update the email for Dinh Nguyen. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCH 3/3] arm: socfpga: Enable saveenv for SD/MMC

From: Dinh Nguyen Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- v2: Move this option to be on a per-board basis Add config for socfpga_cyclone5 and socfpga_arria5 ---

[U-Boot] [PATCH 1/3] arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files

From: Dinh Nguyen Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen

[U-Boot] [PATCH] ARM: socfpga: Enable saveenv for SD/MMC

From: Dinh Nguyen Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- include/configs/socfpga_common.h | 5 + 1 file changed, 5 insertions(+) diff --git

[U-Boot] [PATCHv2] arm: socfpga: Add support for the Terasic DE-0 Atlas board

From: Dinh Nguyen Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen --- v2: add ethernet support moved

[U-Boot] [PATCH] arm: socfpga: Add support for the Terasic DE-0 Atlas board

From: Dinh Nguyen Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is a bit different because it has a KSZ9031 PHY, so for now, ethernet doesn't quite work yet, as a few patches are

[U-Boot] [PATCH] ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS

From: Dinh Nguyen dingu...@opensource.altera.com Fix build error for socfpga_cyclone5_defconfig: board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function) make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1

[U-Boot] [PATCHv4 3/3] arm: socfpga: enable the Altera SDRAM controller driver

From: Dinh Nguyen dingu...@opensource.altera.com Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Marek Vasut ma...@denx.de --- include/configs/socfpga_common.h | 5 + 1 file changed, 5 insertions(+) diff --git

[U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform. v4: - Further cleanup by removing comments that do not apply for Cyclone5. - Removed more unused functions Thanks, Dinh Nguyen (3):

[U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

From: Dinh Nguyen dingu...@opensource.altera.com This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCHv3 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This is V3 of patch series that adds the DDR controller driver for Altera's SoCFPGA platform. V3: - Clean up to address comments from Marek for the calibration portion. V2: - Clean up to address comments from Pavel Thanks, Dinh Nguyen (3):

[U-Boot] [PATCHv3 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

From: Dinh Nguyen dingu...@opensource.altera.com This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCHv3 3/3] arm: socfpga: enable the Altera SDRAM controller driver

From: Dinh Nguyen dingu...@opensource.altera.com Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/configs/socfpga_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_common.h

[U-Boot] [PATCH] git-mailrc: add Dinh Nguyen as a contact for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- doc/git-mailrc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/git-mailrc b/doc/git-mailrc index f0470e6..88fb3f9 100644 --- a/doc/git-mailrc +++

[U-Boot] [U-boot][PATCHv2 3/3] arm: socfpga: enable the Altera SDRAM controller driver

From: Dinh Nguyen dingu...@opensource.altera.com Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/configs/socfpga_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_common.h

[U-Boot] [U-boot][PATCHv2 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

From: Dinh Nguyen dingu...@opensource.altera.com This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen

[U-Boot] [U-boot][PATCHv2 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This is V2 of patch series that adds the DDR controller driver for Altera's SoCFPGA platform. V2: - Clean up to address comments from Pavel Thanks, Dinh Nguyen (3): driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

[U-Boot] [PATCH RESEND 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

From: Dinh Nguyen dingu...@opensource.altera.com This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCH RESEND 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This is a resend of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform. This resend contains a new patch: arm: socfpga: enable the Altera SDRAM controller driver This new patch is necessary for the driver to

[U-Boot] [PATCH RESEND 3/3] arm: socfpga: enable the Altera SDRAM controller driver

From: Dinh Nguyen dingu...@opensource.altera.com Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/configs/socfpga_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_common.h

[U-Boot] [PATCHv4 3/3] arm: socfpga: spl: update peripheral pll for dev kit

From: Dinh Nguyen dingu...@opensource.altera.com commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct value should be 79. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[U-Boot] [PATCHv4 1/3] arm: socfpga: spl: Add s_init stub

From: Dinh Nguyen dingu...@opensource.altera.com Add a stub s_init function in the board file. The reason why the stub function is needed is that most of the work is now being done in board_init_f(), there is no need for the SPL to do anything s_init(). However, since lowlevel_init() is still

[U-Boot] [PATCHv4 2/3] arm: socfpga: spl: add board_init_f to SPL

From: Dinh Nguyen dingu...@opensource.altera.com Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Reviewed-by: Marek Vasut ma...@denx.de --- v4: remove CONFIG_SPL_BUILD and add a comment v3: Move the code from s_init to

[U-Boot] [PATCHv4 0/3] Add SPL support for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hello, The following 3 patches are updates to SPL patches that Marek has already applied to his tree. I have split out the DDR driver patches into a separate patch series to make it more convenient to review. Thanks, Dinh Nguyen (3): arm:

[U-Boot] [U-boot][PATCH 1/2] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

From: Dinh Nguyen dingu...@opensource.altera.com This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen

[U-Boot] [U-boot][PATCH 0/2] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Hello, The following 2 patches adds the DDR controller driver that is in the Altera SoCFPGA platform. This driver is needed for the SPL on the platform. Thanks, Dinh Nguyen (2): driver/ddr/altera: Add DDR driver for Altera's SDRAM controller

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