According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/progra
PL310 is the L2$ controller from ARM used in many SoCs. Before jumping
to linux, UBoot will call v7_outer_cache_disable in
cleanup_before_linux_select to disable L2$. This patch is to support
cache disable of PL310.
Signed-off-by: Haifeng Li
arch/arm/lib/cache-pl310.c | 5 +
1 file changed, 5
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