Re: [PATCH] arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range

Hi Xavier,     Thanks for your patch. On 2022/7/16 18:31, Xavier Drudis Ferran wrote: The original code set up the DDR clock to 48 MHz, not 50MHz as requested, and did it in a way that didn't satisfy the Application Notes in RK3399 TRM [1]. 2.9.2.B says: PLL frequency range requirement

Re: [PATCH] arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range

On Sat, Jul 16, 2022 at 12:31:45PM +0200, Xavier Drudis Ferran wrote: > The original code set up the DDR clock to 48 MHz, not 50MHz as > requested, and did it in a way that didn't satisfy the Application > Notes in RK3399 TRM [1]. 2.9.2.B says: > >PLL frequency range requirement >[...] >

[PATCH] arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range

The original code set up the DDR clock to 48 MHz, not 50MHz as requested, and did it in a way that didn't satisfy the Application Notes in RK3399 TRM [1]. 2.9.2.B says: PLL frequency range requirement [...] FOUTVCO: 800MHz to 3.2GHz 2.9.2.A : PLL output frequency configuration [...