[PATCH] arm: socfpga: n5x: Update DDR init progress bit

[Jit Loon Lim]

From: Tien Fong Chee <tien.fong.c...@intel.com>

The bit[30] of boot scratch cold 8 register is used as DDR init progress
tracking by SDM when watchdog is triggered due to ddr init hang, so that
SDM can run a clean reset to DDR subsystem.

Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon....@intel.com>
---
 drivers/ddr/altera/sdram_n5x.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index 135bc8fd7d..d707bba862 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -428,6 +428,18 @@ enum data_process {
        LOADING
 };
 
+void ddr_init_inprogress(bool start)
+{
+       if (start)
+               setbits_le32(socfpga_get_sysmgr_addr() +
+                            SYSMGR_SOC64_BOOT_SCRATCH_COLD8,
+                            ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK);
+       else
+               clrbits_le32(socfpga_get_sysmgr_addr() +
+                            SYSMGR_SOC64_BOOT_SCRATCH_COLD8,
+                            ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK);
+}
+
 bool is_ddr_retention_enabled(u32 reg)
 {
        if (reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK)
@@ -2848,6 +2860,7 @@ int sdram_mmr_init_full(struct udevice *dev)
 
        if (!is_ddr_init_skipped(reg)) {
                printf("SDRAM init in progress ...\n");
+               ddr_init_inprogress(true);
 
                /*
                 * Polling reset complete, must be high to ensure DDR
@@ -2994,6 +3007,10 @@ int sdram_mmr_init_full(struct udevice *dev)
        priv->info.size = gd->ram_size;
 
        sdram_size_check(&bd);
+
+       /* Marking end of ddr init with passing basic memory test */
+       ddr_init_inprogress(false);
+
        sdram_set_firewall(&bd);
 
        ddr_offset = simple_strtoul(offset, &endptr, 16);
-- 
2.26.2