Re: [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks

On 7/19/23 10:49, Ashok Reddy Soma wrote: gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) d

[PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks

gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/cl