Hi Pali,
I've created a pull request for this patch to the Marvell repo.
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/41
Thanks,
Tony
On Thu, Apr 13, 2023 at 11:06 PM Stefan Roese wrote:
>
> On 4/3/23 06:42, Tony Dinh wrote:
> > - DDR Training sequence happens very fast. Th
On 4/3/23 06:42, Tony Dinh wrote:
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR trainin
Hi Stefan,
On Tue, Apr 11, 2023 at 1:36 AM Stefan Roese wrote:
>
> Hi Tony,
>
> On 4/3/23 06:42, Tony Dinh wrote:
> > - DDR Training sequence happens very fast. The speedup in boot time is
> > negligible by skipping the training sequence during 2nd boot or after.
> > So remove the check and skip.
Hi Tony,
On 4/3/23 06:42, Tony Dinh wrote:
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during D
Hi Pali,
Could you review this patch?
Thanks,
Tony
On Sun, Apr 2, 2023 at 9:42 PM Tony Dinh wrote:
>
> - DDR Training sequence happens very fast. The speedup in boot time is
> negligible by skipping the training sequence during 2nd boot or after.
> So remove the check and skip.
> - This change
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a l
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