Re: [PATCH] k3: pmic: Clear ESM masks

2023-05-04 Thread Tom Rini
On Wed, Apr 05, 2023 at 04:24:35PM +0530, Neha Malcom Francis wrote: > ESM MCU masks must be set to 0h so that PMIC can handle errors > that require attention for example SYS_SAFETY_ERRn. The required bits > must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK. > > If PMIC expec

[PATCH] k3: pmic: Clear ESM masks

2023-04-05 Thread Neha Malcom Francis
ESM MCU masks must be set to 0h so that PMIC can handle errors that require attention for example SYS_SAFETY_ERRn. The required bits must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK. If PMIC expected to handle errors, make sure EVM is configured to connect SOC_SAFETY_ERRz (Ma