Re: [PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

2023-09-28 Thread Yu-Chien Peter Lin
Hi Samuel, On Wed, Sep 27, 2023 at 04:32:30PM -0500, Samuel Holland wrote: > On 9/27/23 02:25, Yu Chien Peter Lin wrote: > > The Andes PLMT driver directly accesses the mtime MMIO region, > > indicating its intended use in the M-mode boot stage. However, > > since U-Boot proper (S-mode) also uses

Re: [PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

2023-09-27 Thread Samuel Holland
On 9/27/23 02:25, Yu Chien Peter Lin wrote: > The Andes PLMT driver directly accesses the mtime MMIO region, > indicating its intended use in the M-mode boot stage. However, > since U-Boot proper (S-mode) also uses the PLMT driver, we need > to specifically mark the region as readable through PMPCF

[PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

2023-09-27 Thread Yu Chien Peter Lin
The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Sme