On 29/12/2020 14:58, Neil Armstrong wrote:
> The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI
> panels, this adds the bindings.
>
> This D-PHY depends on a separate analog PHY.
>
> The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and
> MIPI DSI at the same ti
On Mon, Jan 11, 2021 at 09:47:29AM +0100, Neil Armstrong wrote:
> Hi Simon, Tom,
>
> Could you review patches 1 & 2 of this serie ?
Patches 1 and 2 look fine to me, FWIW.
--
Tom
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Hi Simon, Tom,
Could you review patches 1 & 2 of this serie ?
Thanks,
Neil
On 29/12/2020 14:58, Neil Armstrong wrote:
> The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI
> panels, this adds the bindings.
>
> This D-PHY depends on a separate analog PHY.
>
> The Amlogic AXG MIPI +
The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI
panels, this adds the bindings.
This D-PHY depends on a separate analog PHY.
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and
MIPI DSI at the same time.
In order to configure the DSI PHY timings, a new "co
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