Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.

Signed-off-by: Peng Fan <peng....@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9a039ce127..7fcbd53f30 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -57,7 +57,7 @@ void enable_tzc380(void)
        /* Enable TZASC and lock setting */
        setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
        setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
-       if (is_imx8mm() || is_imx8mn())
+       if (is_imx8mm() || is_imx8mn() || is_imx8mp())
                setbits_le32(&gpr->gpr[10], BIT(1));
        /*
         * set Region 0 attribute to allow secure and non-secure
-- 
2.16.4

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