RISC-V patches are developed for OpenSBI and Linux to replace random boot
by sequential CPU bring-up.
In this scenario the id of the active hart has to be passed from boot stage
to boot stage. Using a UEFI variable would provide an easy implementation.
This patch provides a weak function that is
On 2/5/20 1:28 AM, Atish Patra wrote:
On Sat, Feb 1, 2020 at 8:55 AM Heinrich Schuchardt wrote:
RISC-V patches are developed for OpenSBI and Linux to replace random boot
by sequential CPU bring-up.
In this scenario the id of the active hart has to be passed from boot stage
to boot stage. Usin
On Sat, Feb 1, 2020 at 8:55 AM Heinrich Schuchardt wrote:
>
> RISC-V patches are developed for OpenSBI and Linux to replace random boot
> by sequential CPU bring-up.
>
> In this scenario the id of the active hart has to be passed from boot stage
> to boot stage. Using a UEFI variable would provide
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