Re: [PATCH 1/2] spi: cadence-quadspi: Fix check condition for DTR ops

2023-03-27 Thread Pratyush Yadav
On Thu, Mar 23 2023, Dhruva Gole wrote: > buswidth and dtr fields in spi_mem_op are only valid when the > corresponding spi_mem_op phase has a non-zero length. For example, Right. > SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR > phase. > > Fix the dtr checks in

[PATCH 1/2] spi: cadence-quadspi: Fix check condition for DTR ops

2023-03-23 Thread Dhruva Gole
buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() to ignore empty spi_mem_op phases, as checking for dtr