Re: [PATCH 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote: > > For some reason, on the Mercury+ AA1 module, calling > fpgamgr_wait_early_user_mode immediately after writing the peripheral > bitstream leaves the fpga in a broken state (ddr calibration hangs). > Adding a delay before the first sync word is w

[PATCH 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

For some reason, on the Mercury+ AA1 module, calling fpgamgr_wait_early_user_mode immediately after writing the peripheral bitstream leaves the fpga in a broken state (ddr calibration hangs). Adding a delay before the first sync word is written seems to fix this. Inspecting the fpgamgr registers be