[PATCH 10/17] clk: rk3328: Add get hdmiphy clock

[Jagan Teki]

From: Jagan Teki <ja...@edgeble.ai>

Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.

Signed-off-by: Jagan Teki <ja...@edgeble.ai>
---
 drivers/clk/rockchip/clk_rk3328.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3328.c 
b/drivers/clk/rockchip/clk_rk3328.c
index 7fcf84f08e..5a4a555d36 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -179,6 +179,10 @@ enum {
        CLK_I2C3_DIV_CON_SHIFT          = 8,
        CLK_I2C2_PLL_SEL_SHIFT          = 7,
        CLK_I2C2_DIV_CON_SHIFT          = 0,
+
+       /* CLKSEL_CON40 */
+       CLK_HDMIPHY_DIV_CON_SHIFT       = 3,
+       CLK_HDMIPHY_DIV_CON_MASK        = 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT,
 };
 
 #define VCO_MAX_KHZ    (3200 * (MHz / KHz))
@@ -656,6 +660,16 @@ static ulong rk3328_vop_set_clk(struct rk3328_clk_priv 
*priv,
 }
 #endif
 
+static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru)
+{
+       u32 div, con;
+
+       con = readl(&cru->clksel_con[40]);
+       div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT;
+
+       return DIV_TO_RATE(GPLL_HZ, div);
+}
+
 static ulong rk3328_clk_get_rate(struct clk *clk)
 {
        struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -685,6 +699,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
        case SCLK_SPI:
                rate = rk3328_spi_get_clk(priv->cru);
                break;
+       case PCLK_HDMIPHY:
+               rate = rk3328_hdmiphy_get_clk(priv->cru);
+               break;
        default:
                return -ENOENT;
        }
-- 
2.25.1