Re: [PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

Hi Quentin, On 2024-04-02 16:44, Quentin Schulz wrote: > Hi Jonas, > > On 3/31/24 22:28, Jonas Karlman wrote: >> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the >> SCLK_PCIEPHY_REF clock. >> >> The existing enable/disable ops for SCLK_PCIEPHY_REF already handles >>

Re: [PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

On 2024/4/1 04:28, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate

Re: [PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default

[PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock. Add dummy support for