Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

> > From: Bin Meng > > Sent: Monday, June 12, 2023 3:36 PM > > To: u-boot@lists.denx.de > > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) > > > > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to > > support aclint &

Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

> From: Bin Meng > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot@lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to > support aclint > > This RISC-V ACLINT specification

[PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specificati