Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit
f4d51dffc6c0 ("Linux 5.9-rc4")
Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
---
arch/arm/dts/r8a774a1.dtsi | 10 +-
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 96 +++++++++----------
include/dt-bindings/power/r8a774a1-sysc.h | 2 -
3 files changed, 51 insertions(+), 57 deletions(-)
diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi
index a603d94797..8e80f50132 100644
--- a/arch/arm/dts/r8a774a1.dtsi
+++ b/arch/arm/dts/r8a774a1.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
+#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
+
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
@@ -2250,7 +2252,7 @@
status = "disabled";
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@@ -2262,7 +2264,7 @@
status = "disabled";
};
- sdhi1: sd@ee120000 {
+ sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@@ -2274,7 +2276,7 @@
status = "disabled";
};
- sdhi2: sd@ee140000 {
+ sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@@ -2286,7 +2288,7 @@
status = "disabled";
};
- sdhi3: sd@ee160000 {
+ sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
index ac3fde148c..67bf8cdf49 100644
--- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -10,56 +10,50 @@
/* r8a774a1 CPG Core Clocks */
#define R8A774A1_CLK_Z 0
#define R8A774A1_CLK_Z2 1
-#define R8A774A1_CLK_ZR 2
-#define R8A774A1_CLK_ZG 3
-#define R8A774A1_CLK_ZTR 4
-#define R8A774A1_CLK_ZTRD2 5
-#define R8A774A1_CLK_ZT 6
-#define R8A774A1_CLK_ZX 7
-#define R8A774A1_CLK_S0D1 8
-#define R8A774A1_CLK_S0D2 9
-#define R8A774A1_CLK_S0D3 10
-#define R8A774A1_CLK_S0D4 11
-#define R8A774A1_CLK_S0D6 12
-#define R8A774A1_CLK_S0D8 13
-#define R8A774A1_CLK_S0D12 14
-#define R8A774A1_CLK_S1D1 15
-#define R8A774A1_CLK_S1D2 16
-#define R8A774A1_CLK_S1D4 17
-#define R8A774A1_CLK_S2D1 18
-#define R8A774A1_CLK_S2D2 19
-#define R8A774A1_CLK_S2D4 20
-#define R8A774A1_CLK_S3D1 21
-#define R8A774A1_CLK_S3D2 22
-#define R8A774A1_CLK_S3D4 23
-#define R8A774A1_CLK_LB 24
-#define R8A774A1_CLK_CL 25
-#define R8A774A1_CLK_ZB3 26
-#define R8A774A1_CLK_ZB3D2 27
-#define R8A774A1_CLK_ZB3D4 28
-#define R8A774A1_CLK_CR 29
-#define R8A774A1_CLK_CRD2 30
-#define R8A774A1_CLK_SD0H 31
-#define R8A774A1_CLK_SD0 32
-#define R8A774A1_CLK_SD1H 33
-#define R8A774A1_CLK_SD1 34
-#define R8A774A1_CLK_SD2H 35
-#define R8A774A1_CLK_SD2 36
-#define R8A774A1_CLK_SD3H 37
-#define R8A774A1_CLK_SD3 38
-#define R8A774A1_CLK_SSP2 39
-#define R8A774A1_CLK_SSP1 40
-#define R8A774A1_CLK_SSPRS 41
-#define R8A774A1_CLK_RPC 42
-#define R8A774A1_CLK_RPCD2 43
-#define R8A774A1_CLK_MSO 44
-#define R8A774A1_CLK_CANFD 45
-#define R8A774A1_CLK_HDMI 46
-#define R8A774A1_CLK_CSI0 47
-#define R8A774A1_CLK_CSIREF 48
-#define R8A774A1_CLK_CP 49
-#define R8A774A1_CLK_CPEX 50
-#define R8A774A1_CLK_R 51
-#define R8A774A1_CLK_OSC 52
+#define R8A774A1_CLK_ZG 2
+#define R8A774A1_CLK_ZTR 3
+#define R8A774A1_CLK_ZTRD2 4
+#define R8A774A1_CLK_ZT 5
+#define R8A774A1_CLK_ZX 6
+#define R8A774A1_CLK_S0D1 7
+#define R8A774A1_CLK_S0D2 8
+#define R8A774A1_CLK_S0D3 9
+#define R8A774A1_CLK_S0D4 10
+#define R8A774A1_CLK_S0D6 11
+#define R8A774A1_CLK_S0D8 12
+#define R8A774A1_CLK_S0D12 13
+#define R8A774A1_CLK_S1D2 14
+#define R8A774A1_CLK_S1D4 15
+#define R8A774A1_CLK_S2D1 16
+#define R8A774A1_CLK_S2D2 17
+#define R8A774A1_CLK_S2D4 18
+#define R8A774A1_CLK_S3D1 19
+#define R8A774A1_CLK_S3D2 20
+#define R8A774A1_CLK_S3D4 21
+#define R8A774A1_CLK_LB 22
+#define R8A774A1_CLK_CL 23
+#define R8A774A1_CLK_ZB3 24
+#define R8A774A1_CLK_ZB3D2 25
+#define R8A774A1_CLK_ZB3D4 26
+#define R8A774A1_CLK_CR 27
+#define R8A774A1_CLK_CRD2 28
+#define R8A774A1_CLK_SD0H 29
+#define R8A774A1_CLK_SD0 30
+#define R8A774A1_CLK_SD1H 31
+#define R8A774A1_CLK_SD1 32
+#define R8A774A1_CLK_SD2H 33
+#define R8A774A1_CLK_SD2 34
+#define R8A774A1_CLK_SD3H 35
+#define R8A774A1_CLK_SD3 36
+#define R8A774A1_CLK_RPC 37
+#define R8A774A1_CLK_RPCD2 38
+#define R8A774A1_CLK_MSO 39
+#define R8A774A1_CLK_HDMI 40
+#define R8A774A1_CLK_CSI0 41
+#define R8A774A1_CLK_CP 42
+#define R8A774A1_CLK_CPEX 43
+#define R8A774A1_CLK_R 44
+#define R8A774A1_CLK_OSC 45
+#define R8A774A1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a774a1-sysc.h
b/include/dt-bindings/power/r8a774a1-sysc.h
index d84ea0eb12..d35183557c 100644
--- a/include/dt-bindings/power/r8a774a1-sysc.h
+++ b/include/dt-bindings/power/r8a774a1-sysc.h
@@ -18,12 +18,10 @@
#define R8A774A1_PD_CA53_CPU2 7
#define R8A774A1_PD_CA53_CPU3 8
#define R8A774A1_PD_CA57_SCU 12
-#define R8A774A1_PD_CR7 13
#define R8A774A1_PD_A3VC 14
#define R8A774A1_PD_3DG_A 17
#define R8A774A1_PD_3DG_B 18
#define R8A774A1_PD_CA53_SCU 21
-#define R8A774A1_PD_A3IR 24
#define R8A774A1_PD_A2VC0 25
#define R8A774A1_PD_A2VC1 26
--
2.17.1
