On Mon, 24 Jan 2022 20:47:30 -0600
Samuel Holland wrote:
Hi Samuel,
many thanks for having a look!
> On 1/24/22 7:15 PM, Andre Przywara wrote:
> > According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
> > ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
On 1/24/22 7:15 PM, Andre Przywara wrote:
> According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
> ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
> maintenance operations are done. As we do those things still in start.S,
> we need to move the SMPEN bit
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.
This introduces a new ARMv7
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