RE: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

Hi Vladimir, Thanks a lot for your comments! > -Original Message- > From: Vladimir Oltean > Sent: 2020年5月3日 22:07 > To: Z.q. Hou > Cc: u-boot ; Joe Hershberger > ; Bin Meng ; Priyanka > Jain > Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the >

Re: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

ershberger > > ; Bin Meng ; Priyanka > > Jain > > Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the > > corresponding MII > > > > On Sun, 3 May 2020 at 09:28, Zhiqiang Hou > > wrote: > > > > > > From: Hou Zhiqiang > > > &

RE: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

Hi Vladimir, Thanks a lot for your review and test! > -Original Message- > From: Vladimir Oltean > Sent: 2020年5月3日 19:35 > To: Z.q. Hou > Cc: u-boot ; Joe Hershberger > ; Bin Meng ; Priyanka > Jain > Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through

Re: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

On Sun, 3 May 2020 at 09:28, Zhiqiang Hou wrote: > > From: Hou Zhiqiang > > When an eTSEC is configured to use TBI, configuration of the > TBI is done through the MIIM registers for that eTSEC. > For example, if a TBI interface is required on eTSEC2, then > the MIIM registers starting at offset 0

[PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

From: Hou Zhiqiang When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: t