This change allows to understand how are Preliminary Base and Option
registers configured and later fix improper configuration.
Signed-off-by: Pali Rohár <p...@kernel.org>
---
include/configs/P2041RDB.h | 7 ++++---
include/configs/corenet_ds.h | 8 +++++---
include/configs/p1_p2_rdb_pc.h | 11 ++++++++---
3 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 687b88bd2abd..c2d7c76f6063 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -118,7 +118,8 @@
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
BR_PS_16 | BR_V)
#define CONFIG_SYS_FLASH_OR_PRELIM \
- ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+ (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS | OR_GPCM_TRLX | OR_GPCM_EAD \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
#define CONFIG_FSL_CPLD
@@ -162,11 +163,11 @@
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K
*/ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 9108f206b696..c908269b24c7 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -117,7 +117,9 @@
#define CONFIG_SYS_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
| BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY &
~OR_GPCM_EHTR) \
+#define CONFIG_SYS_FLASH_OR_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | \
+ | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+ | OR_GPCM_TRLX | OR_GPCM_EAD \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_BR1_PRELIM \
@@ -164,11 +166,11 @@
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K
*/ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 9726ef3077f7..b567eb1a03cc 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -243,7 +243,10 @@
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+#define CONFIG_FLASH_OR_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
@@ -268,7 +271,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
@@ -325,7 +328,9 @@
/* CPLD config size: 1Mb */
#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
BR_PS_8 | BR_V)
-#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
+#define CONFIG_CPLD_OR_PRELIM (OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_PMC_BASE 0xff980000
#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
--
2.20.1
