On Mon, May 18, 2020 at 06:45:17PM +, Heinrich Schuchardt wrote:
> Am May 18, 2020 6:30:09 PM UTC schrieb Tom Rini :
> >On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
> >> [Also adding Tom Rini as ARM maintainer]
> >>
> >> Am 2020-05-14 22:17, schrieb Alexander Graf:
> >> > On
Am May 18, 2020 6:30:09 PM UTC schrieb Tom Rini :
>On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
>> [Also adding Tom Rini as ARM maintainer]
>>
>> Am 2020-05-14 22:17, schrieb Alexander Graf:
>> > On 14.05.20 20:46, Heinrich Schuchardt wrote:
>> > > On 5/14/20 2:38 PM, Michael Wal
On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
> [Also adding Tom Rini as ARM maintainer]
>
> Am 2020-05-14 22:17, schrieb Alexander Graf:
> > On 14.05.20 20:46, Heinrich Schuchardt wrote:
> > > On 5/14/20 2:38 PM, Michael Walle wrote:
> > > > On some architectures, specifically th
[Also adding Tom Rini as ARM maintainer]
Am 2020-05-14 22:17, schrieb Alexander Graf:
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary
cores
wait for an interrupt before entering the spin-ta
Am 2020-05-14 22:17, schrieb Alexander Graf:
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary
cores
wait for an interrupt before entering the spin-tables. This applies
only
to boards which d
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot
On 5/14/20 2:38 PM, Michael Walle wrote:
> On some architectures, specifically the layerscape, the secondary cores
> wait for an interrupt before entering the spin-tables. This applies only
> to boards which doesn't have PSCI provided by TF-a and u-boot does the
%s/TF-a/TF-A/, %s/u-boot/U-Boot/
>
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot does the
secondary cores handling.
bootm/booti already call that function for ARM architectu
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