On 2023/4/17 17:19, Eugen Hristev wrote:
From: Jon Lin
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin
[kever.y...@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang
Signed-off-by: Kever Yang
[eugen.hris...@collabora.com: s
From: Jon Lin
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin
[kever.y...@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang
Signed-off-by: Kever Yang
[eugen.hris...@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hriste
2 matches
Mail list logo