Re: [PATCH 4/7] spi: dw: Force set K210 fifo length to 31

On 2/15/22 11:16 AM, Niklas Cassel wrote: From: Damien Le Moal The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects. However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error

[PATCH 4/7] spi: dw: Force set K210 fifo length to 31

From: Damien Le Moal The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects. However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this problem by force setting