On 2023/2/14 06:27, Chris Morgan wrote:
From: Chris Morgan
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.
Signed-off-by: Peter Geis
Signed-off-by: Chris M
From: Chris Morgan
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.
Signed-off-by: Peter Geis
Signed-off-by: Chris Morgan
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arch/arm/mach-rockchip/rk3568/rk
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